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Participant bhanu27
Participant
151 Views
Registered: ‎05-10-2019

Post implementation sim for Zynq MPSoC+

Hi,

 

I am using Zynq UltraScale+ MPSoC Verification IP v1.0 for behavioral simulation.

For Post implementation timing simulation, It seems that the Zynq VIP

cannot be used. Any suggestions or workarounds on how to do post implementation timing

simulation for Zynq MPSoC

 

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1 Reply
Xilinx Employee
Xilinx Employee
78 Views
Registered: ‎07-16-2019

Re: Post implementation sim for Zynq MPSoC+

Hi, 

There is a similiar problem and solution found here:

https://forums.xilinx.com/t5/Simulation-and-Verification/MPSoC-Verification-IP-Post-Synthesis-Post-Implementation/td-p/820843

"The verification IP is removed from the design for synthesis and implementation. It cannot be used for post-synthesis/implementation simulations"

"The MPSoC VIP only simulates AXI transfers. It does not provide a way to generate traffic from the GEM Ethernet controller"

"You might try @muzaffer's suggestion in this post if gate simulation is important to you:

https://forums.xilinx.com/t5/Simulation-and-Verification/Using-AXI-BFM-in-post-synthesis-implementation-simulations/td-p/783671

 

Hope that helps!

Ebrahim

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