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Registered: ‎11-05-2019

Post implementation simulation Error - LUT does not generate the expected output

Dear all,

I have a problem with post implementation simulation of my design. I tested the implemented design on a FPGA board (PYNQ) and it works perfectly but with the same testbench, the post implementation simulation does not produce the same answer. 

As you see, the ready_reg_i_1 is generated by a LUT5:

Post implementation codePost implementation code

Here the truth table of the same LUT5 is shown:
LUT truth tableLUT truth table

I expected when the inputs of the LUT are "11011", the output (ready_reg_i_1_n_0) becomes '1' but as you can see in below, the output is '0'.
Simulation waveformSimulation waveform

Can someone please explain it to me what do I do wrong? And why the post implementation simulation does not match the implemented design on PYNQ board. The clock frequency for simulation and running design on the board is 100 MHz where the maximum delay path is ~8.5 ns.



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Registered: ‎09-15-2016

Hi @brazi_perjikolaei ,

Did you run post-implementation functional simulation for your design? Do you see the same behaviour ?

Can you please share the project to check this issue at our end?

Thanks & Regards,
Sravanthi B
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