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Newbie leepoult
Newbie
156 Views
Registered: ‎01-29-2019

Post netlist simulation for FPGA debugging; how can I pre-load a file into FPGA block memory?

Hello,

I'm doing post-netlist simulation with place&routed netlist and SDF from Vivado.

I use VCS for simulator and I can successfully compiled my netlist and SDF.

But I got an error when I trying to upload a MIF(or axf, it is a firmware) into the block ram.

Actually I've done this process in RTL level simulation.

I got a CPU core in my design and I need to upload a compiled firmware file into the code area block ram.

I don't know how can I put it in... I've found "uploadmem, data2mem" methodolgy on the web.

But it seems not for the simulation.

Anyone know about this?

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2 Replies
Moderator
Moderator
76 Views
Registered: ‎04-24-2013

Re: Post netlist simulation for FPGA debugging; how can I pre-load a file into FPGA block memory?

Hi @leepoult,

 

Have a look at the following post that may help.

https://forums.xilinx.com/t5/Simulation-and-Verification/Initializing-block-RAM-for-simulation/m-p/857776#M22260

Best Regards
Aidan

 

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Newbie leepoult
Newbie
35 Views
Registered: ‎01-29-2019

Re: Post netlist simulation for FPGA debugging; how can I pre-load a file into FPGA block memory?

Above link, that may helpful if I use RTL level sim.

Actually I've already use "readmemh" when I simulate in RTL level.

But it's impossible with post-netlist because I got only one big huge netlist file and there are splited block memories, LUT and other basic components of FPGA.

For example, I made one 128x64 spsram memory using block memory gen. but I got lots of distributed (splited) BRAMs and LUTs and others on my netlist.

 

I know how to insert pre-compiled code into the bit file.

But I don't know how can I put it into the post-routed-netlist.

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