cancel
Showing results for 
Search instead for 
Did you mean: 
Observer
Observer
98 Views
Registered: ‎05-04-2016

Post-route simulation doesn't match hardware

I am chasing a weird bug.  I have a design with 4 identical banks of 4 cascaded low-pass decimation filters, using the Xilinx FIR generator.  Each filter in the chain can be individually bypassed.

In simulation all of the filters behave as expected. 

In hardware I inject a synthetic signal into each filter, one at a time.  I am putting the same signal into each bank. At the output of the system,  I can see that the first two filters in the chain do not have the expected filter response:

  • The first two filters have different results from boot to boot
    • The results are identical during the same power cycle.
  • Each filter bank has different (but all poor) results, even though they are the result of a for-generate loop.
  • The second two filters behave as expected

My first thought was that there was a synthesis optimization problem.  However, I spent considerable time setting up a post-route simulation, and the results look great even in the post-route sim.

I have tested on different boards, and both have the same issue with the first two filters.  Therefore I am ruling out hardware/chip problems.

 

My questions are:

  • Why do the filter banks differ from each other?
  • Why does the behavior change after a power cycle?

And most importantly:

  • Where do I go from here?

Any ideas about what might be going on?  What can I look at to try to debug this?

0 Kudos