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187 Views
Registered: ‎01-15-2019

Post route simulation

Hi,

I'm using following setup for a project

1)Board name SP06(xc6slx45t-3fgg484)

2)IDE Xilinx ISE 14.7

3)OS -Windows xp

Problem Statement

I'm feeding 16 bit data as an input with ref clock of 159Mhz and reading the same data at posedge of the clock and i find input data and output data are not same.

I have attached top module as well as testbench to this query,Please help me slove this issue

 

Regards 

Akarsh

Screenshot_1.png
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Registered: ‎06-21-2017

There are two obvious possibilities.  Timing is the more likely problem.  Does your design have timing constraints and does the design meet these constraints?  Does the test bench accurately model the timing of your input signal?

The second possibility is less likely but should be considered.  Are your process sensitivity lists in the VHDL correct?  A behavior simulation uses the process sensitivity list to determine when to model a transaction.  The routed simulation is a hardware model and does not use the process sensitivity list, so an incorrect list could cause differences between the simulations.

Still, timing is the first thing to look at.  159MHz is fairly fast for a Spartan6 and you need to be careful here.

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