11-04-2015 05:54 AM
I wonder who could give me a detailed documents on post/timing simulation in vivado.
i only found the ug900 which take some general simulation introduction.
what i want to do is do the post simulation and timing simulation in vivado, and i could load the post-implementation timing in vivado, but i found the simulation waveform is the same as behavior simulation. how did i found if there exist a potentationly timing issue in waveform or report?
Thank you. very very much.
11-04-2015 06:13 AM
If the post-implementation timing report has no violations and if the post-implementation timing simulation is functionally identical to your behavioural simulation(i.e as expected),
Then you are good to go. The performance of your design post-device programming will most certainly be as expected.
11-04-2015 09:31 AM
In the Vivado GUI, when you click on "Run Simulation", you get several options. Choose the post-synthesis or post-implementation timing simulation.
11-13-2015 10:17 PM
Thank you. though i could launch the post simulation, and continue run the behavior test bench in this post simulation envrioment, but i didn't i could check the post simulation result?
for example, if the cpu core execute the read/write operation in post timing simulation, i could check the memory/general register if the opeartion work correctlly in behavior operation, but how did i could check the post simualation? also the if the memory/general register's reslut is OK?
Thank you so much.