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Participant
Participant
8,312 Views
Registered: ‎03-26-2013

Post timing simulation in vivado

I wonder who could give me a detailed documents on post/timing simulation in vivado.

i only found the ug900 which take some general simulation introduction.

what i want to do is do the post simulation and timing simulation in vivado, and i could load the post-implementation timing in vivado, but i found the simulation waveform is the same as behavior simulation. how did i found if there exist a potentationly timing issue in waveform or report?

Thank you. very very much.

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Xilinx Employee
Xilinx Employee
8,306 Views
Registered: ‎05-07-2015

Re: Post timing simulation in vivado

HI @zxm02370303

If the post-implementation timing report has no violations and if the post-implementation timing simulation is functionally identical to your behavioural simulation(i.e as expected),

Then you are good to go. The performance of your design post-device programming will most certainly be as expected.

Thanks
Bharath
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Guide
Guide
8,288 Views
Registered: ‎01-23-2009

Re: Post timing simulation in vivado

In the Vivado GUI, when you click on "Run Simulation", you get several options. Choose the post-synthesis or post-implementation timing simulation.

 

Avrum

 

RunSim.jpg

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Participant
Participant
8,241 Views
Registered: ‎03-26-2013

Re: Post timing simulation in vivado

Thank you. though i could launch the post simulation, and continue run the behavior test bench in this post simulation envrioment, but i didn't i could check the post simulation result?

for example, if the cpu core execute the read/write operation in post timing simulation, i could check the memory/general register if the opeartion work correctlly in behavior operation, but how did i could check the post simualation? also the if the memory/general register's reslut is OK?

Thank you so much.

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