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Contributor
Contributor
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Registered: ‎01-06-2016

Predefined constant for simulation

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Is there a predefined constant that indicates simulation is running? I'd like to be able to make code dependent on this rather than having to change all the defined SIM constants in multiple files.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Predefined constant for simulation

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Right, it's for simulation.

For synthesis, macro SYNTHESIS is internally 1 in vivado synthesis.

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Scholar
Scholar
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Registered: ‎08-01-2012

Re: Predefined constant for simulation

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What sim constants are you referring to? what language? what tool?

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Contributor
Contributor
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Registered: ‎01-06-2016

Re: Predefined constant for simulation

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The tool in use is the Vivado 18.3 built in simulator. The language is SystemVerilog. I'm assuming there are some built in constant for which I haven't been able to find documentation on. For instance the C pre-processor has __FILE__ etc.Does SystemVerilog or the simulator have similar constants? I assume the predefined constants would be generic to multiple simulators / languages.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Predefined constant for simulation

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Below is from UG900.

XILINX_SIMULATOR is a Verilog predefined-macro. The value of this macro is 1.
Predefined macros perform tool-specific functions, or identify which tool to use in a design flow. The following is an example usage:
`ifdef VCS
// VCS specific code
`endif
`ifdef INCA
// NCSIM specific code
`endif
`ifdef MODEL_TECH
// MODELSIM specific code
`endif
`ifdef XILINX_ISIM
// ISE Simulator (ISim) specific code
`endif
`ifdef XILINX_SIMULATOR
// Vivado Simulator (XSim) specific code
`endif

Is this what you're looking for?

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Contributor
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Registered: ‎01-06-2016

回复: Predefined constant for simulation

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It may be what I'm looking for.

Is the XILINX_SIMULATOR constant only defined during simulation (and not during synthesis)?

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Predefined constant for simulation

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Right, it's for simulation.

For synthesis, macro SYNTHESIS is internally 1 in vivado synthesis.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

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