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Registered: ‎01-29-2020

Problem in tools flow Vivado(IPI) - HDL Designer - Modelsim

I'm working with design which includes Native FIFO created in FIFO Generator 13.2. I included generated files in project, but in HDL Designer - Design Manager - Design Hierarchy view unbound component is shown001.jpg

Also the attempt to run simulation in Modelsim was unsuccessful - Modelsim aborted with following message: "# Loading NGTS_Ref_Design.wadj_fifo_fifo_generator_0_0
# ** Error: (vsim-3033) C:/DEV/Hensoldt/FW/NGTS_Ref_Design/xipi/wadj_fifo/ip/wadj_fifo_fifo_generator_0_0/sim/wadj_fifo_fifo_generator_0_0.v(295): Instantiation of 'fifo_generator_v13_2_3' failed. The design unit was not found."

In the design the following libraries are included:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

Please assist...

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

It looks either you didn't load the pre-compiled IP library, or you didn't compile the IP static file at run time.

If you create your simulation script on your own, it's error prone especially for IPs involved. You need to ensure all the necessary files are compiled, and are compiled to the correct libraries.

I'd suggest that you do export simulation from within the Vivado GUI for the IPI project (Files > Export > Export Simulation). This will generate simulation script that you can take as a reference or run directly.

Please ensure you've firstly compiled simulation libraries for the specific Modelsim version successfully with compile_simlib.

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