I am currently targetting a Virtex-5 FPGA (LT30T) for my current project. In this design, I am using a GTP port running at 2.125 Gbps and 2 DDR2 SDRAM Controller running at 212.5MHz. The GTP port has been created using RocketIO Wizard and the DDR2 SDRAM controller using the lastest MIG tools. I am using ISE 10.1 with all updates and I am using ModelsimPE with a MIXTE language (Verilog/VHDL) license. Note: I invoke Modelsim from ISE project navigator (all simulation files have been added to the source window).
From the beginning of the project, I am being fighting with ModelsimPE to simulate my project (I never has this problem before, but before I was only using a VHDL license of ModelsimPE).
First of all, is there something special to do when working in Mixte language and using SecureIP/Unisim models?