03-19-2013 09:28 AM
I'm having trouble simulating my verilog file, axi_master_bfm_v.v, which contains an instance of cdn_axi4_master_bfm from the secureip library.
I have compiled all Xilinx libraries for VCS using compxlib, and I see the cdn_axi4_master_bfm.vp file in this install directory: $XILINX/secureip/vcs/axi_bfm_vcs/
I followed the directions here: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/sim.pdf on page 170 about using VCS to compile secureip. (I added the +v2k and -lca switches as appropriate).
vcs +v2k -f $XILINX/secureip/vcs/axi_bfm_vcs/axi_bfm_cell.list.f\
-y $XILINX/verilog/src/unisims -y $XILINX/verilog/src/xilinxcorelib \
+incdir+$XILINX/verilog/src +libext+.v $XILINX/verilog/src/glbl.v \
-lca -Mupdate -R axi_master_bfm_v.v
When I run the above, I keep getting this error message:
"Parsing design file '/gsa/ausgsa-p14/00/a3synapse/tool/xilinx_tools/14.2/ISE_DS/ISE/secureip/vcs/axi_bfm_vcs/cdn_axi3_master_bfm.vp'
Error-[STASKEC_USF] Undefined system function
Parsing design file '/gsa/ausgsa-p14/00/a3synapse/tool/xilinx_tools/14.2/ISE_DS/ISE/secureip/vcs/axi_bfm_vcs/cdn_axi3_slave_bfm.vp'
Parsing design file '/gsa/ausgsa-p14/00/a3synapse/tool/xilinx_tools/14.2/ISE_DS/ISE/secureip/vcs/axi_bfm_vcs/cdn_axi4_lite_master_bfm.vp'
Parsing design file '/gsa/ausgsa-p14/00/a3synapse/tool/xilinx_tools/14.2/ISE_DS/ISE/secureip/vcs/axi_bfm_vcs/cdn_axi4_lite_slave_bfm.vp'
Parsing design file '/gsa/ausgsa-p14/00/a3synapse/tool/xilinx_tools/14.2/ISE_DS/ISE/secureip/vcs/axi_bfm_vcs/cdn_axi4_master_bfm.vp'
Parsing design file '/gsa/ausgsa-p14/00/a3synapse/tool/xilinx_tools/14.2/ISE_DS/ISE/secureip/vcs/axi_bfm_vcs/cdn_axi4_slave_bfm.vp'
Parsing design file '/gsa/ausgsa-p14/00/a3synapse/tool/xilinx_tools/14.2/ISE_DS/ISE/secureip/vcs/axi_bfm_vcs/cdn_axi4_streaming_master_bfm.vp'
Parsing design file '/gsa/ausgsa-p14/00/a3synapse/tool/xilinx_tools/14.2/ISE_DS/ISE/secureip/vcs/axi_bfm_vcs/cdn_axi4_streaming_slave_bfm.vp'
Parsing design file '/gsa/ausgsa-p14/00/a3synapse/tool/xilinx_tools/14.2/ISE_DS/ISE/verilog/src/glbl.v'
Parsing design file 'axi_master_bfm_v.v'
Parsing included file 'axi_bfm_defines.vh'.
CPU time: .112 seconds to compile"
Due to the above error (in red), I don't get a "simv" generated, and I cannot simulate the design.
It doesn't matter that the error is reported on cdn_axi3_master_bfm.vp and I'm sourcing cdn_axi4_master_bfm.vp.
Even if I change the cell.lisf.f to have only cdn_axi4_master_bfm.vp defined, I still get the same error.
I'm wondering if this might be because the AXI_BFM directory needs extra permissions I don't have (even though I do have the .vp files in my install)?
I ask this because the master secureip list at $XILINX/secureip/vcs/vcs_secureip_cell.list.f doesn't include $XILINX/secureip/vcs/axi_bfm_vcs/axi_bfm_cell.list.f in the list (although this file exists and point to existing .vp files).
Can someone please help??? Thank you.
07-26-2013 12:12 PM
Did you find a resolution to this problem?
In my case I am using ISE 14.6 and simulating with Modelsim DE 10.2b but get the following error:
# Loading work.cdn_axi4_lite_master_bfm_wrap
# ** Warning: (vsim-PLI-3003) nofile(36): [TOFD] - System task or function '$xilinx_lic_check' is not defined.
# Region: /testbench/TB_model_axi4/axi4_lite_master/cdn_axi4_lite_master_bfm_inst
Prior to finding your post, I too had discovered that the AXI BFM components do not get compiled into the secureip library though their source files are in the ISE install folder. As in your findings, my "mti_secureip_cell.list.f" does not contain the "-f $XILINX/secureip/mti/axi_bfm_mti/axi_bfm_cell.list.f" entry so I suspect they never get compiled by the Simulation Library Compilation Wizard, thus, they don't show up in the ".cxl.verilog.secureip.secureip.nt.cmf" file.
In addition, I have discovered ISE 13.2's version of file "mti_secureip_cell.list.f" does include the "-f $XILINX/secureip/mti/axi_bfm_mti/axi_bfm_cell.list.f". After running the compilation wizard, I see that the AXI BFM components appear to have been compiled as they are listed in the ".cxl.verilog.secureip.secureip.nt.cmf".
For anyone wondering, I do have the Xilinx_AXI_BFM license feature and listed in the License Configuration Manager. I suspect even if I did not have the license, the secureip library should still be compiled with the AXI BFM components as http://www.xilinx.com/support/answers/41497.htm states they are part of ISE as of ISE 13.1. I have also tried the -PLI switch for vsim, but that gives me an error relating to not finding the dependant library; The above AR also states this is no longer required.
I get the same error with ISE 13.2 and thus suspect this may not necessarily be my only problem if even a problem. There maybe somthing else I'm missing.
If anyone has any possible solutions or ideas that could help get me past this point, please share them.
08-12-2013 06:08 PM
Just a quick update...
After numerous install/uninstall cycles of different versions/combinations of ISE and Modelsim (PE,DE,SE,32b,64b,etc) it appears that the final solution that allowed me to simulate the AXI BFM components using Modelsim in Windows 7 is as follows:
1) add the path of the libxil_vsim.dll directly to the PATH environmental variable
2) modified the mti_secureip_cell.list.f file to include -f $XILINX/secureip/mti/axi_bfm_mti/axi_bfm_cell.list.f and re-run the Simulation Library Compilation Wizard as I mentioned above, or manually explicitly compile the AXI BFM related secureip source files as mentioned in AR56087
3) use the -pli libxil_vsim.dll parm switch with the vsim execution even though AR41497 clearly states it is no longer required beyond ISE 13.1.
I have verified that with the changes described in these three items, I can now run AXI BFM simulations with Modelsim PE & DE 10.1b and 10.2b using the source files in ISE 14.5 in Windows 7.
I hope this helps someone else.
04-17-2014 06:27 PM
Please refer to the following reply and see if it helps.