08-11-2019 08:09 PM
I'm tried to simulate a block design with AXI VIP to check if the protocol is correct but when i use the pkg "axi_vip_pkg.sv" i receive this message.
"Unable to open file '' because file does not have read permission. Would you like to open the directory instead?"
The problem is this path /wrk/2018.3/nightly/2018_12_06_2405991/packages/customer/vivado/data/xilinx_vip/hdl/axi_vip_pkg.sv:14954. I tried create that folders and put the file here but the problem persist. I don't know what is the problem. I usign Vivado 2018.3 in Ubuntu 16.02.
Any help is grateful.
08-13-2019 04:44 AM
10-29-2019 06:53 AM
I have the same problem. Also with a BlockMemoryGenerator IP.
For this IP, the simulator creates a ipshared directory structure and puts some files in it. One of the files is named "blk_mem_gen_v8_4.v". This is the file that the simulator is unable to open although it has NO read restrictions as the simulator states.
Besides this is a Verilog file, the rest of my design is written in VHDL. Can this be a hint what went wrong?
All the other IPs dont show this behaviour.