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Newbie
Newbie
748 Views
Registered: ‎06-01-2019

Problem when simulation tried to simulate with axi VIP

Hi,

I'm tried to simulate a block design with AXI VIP to check if the protocol is correct but when i use the pkg "axi_vip_pkg.sv" i receive this message.

"Unable to open file '' because file does not have read permission. Would you like to open the directory instead?"

The problem is this path /wrk/2018.3/nightly/2018_12_06_2405991/packages/customer/vivado/data/xilinx_vip/hdl/axi_vip_pkg.sv:14954. I tried create that folders and put the file here but the problem persist. I don't know what is the problem. I usign Vivado 2018.3 in Ubuntu 16.02.

Any help is grateful.

Regards,

Tomas Kromer

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4 Replies
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Visitor
Visitor
712 Views
Registered: ‎09-23-2018

Hi Thomas,
I have a problem verry simular to yours. In my case it is a block_memory_generator instead of axi_vip_pkg. Did you find a solution?
regards,
Flo
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Newbie
Newbie
699 Views
Registered: ‎06-01-2019

Hi Flo,

No, I change the VIP for AXI protocol checker IP. 

Regards,

Tomás 

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Participant
Participant
550 Views
Registered: ‎08-02-2013

I have the same problem. Also with a BlockMemoryGenerator IP.

For this IP, the simulator creates a ipshared directory structure and puts some files in it. One of the files is named "blk_mem_gen_v8_4.v". This is the file that the simulator is unable to open although it has NO read restrictions as the simulator states.

Besides this is a Verilog file, the rest of my design is written in VHDL. Can this be a hint what went wrong?

All the other IPs dont show this behaviour.

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Scholar
Scholar
161 Views
Registered: ‎12-07-2018

Hello, did you solve this problem? I have the same problem. 

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