12-16-2016 09:28 AM
So I discovered that in 2016.3, the Vivado simulator uses the VHDL 2008 library versions for all files, even those that are not of type 2008. This means that if any VHDL files are incompatible with 2008 (as was my case) that simulation fails with compile errors. A proposed workaround is to use the -93_mode flag which forces the entire design to VHDL 93. (see this thread)
The trouble is that when I add the -93_mode to xsim.compile.xvhdl.more_options, the simulator fails with error VRFC 10-113 and reports that "sim_1/behav/xsim.dir/osc/osc_tb.vdb needs to be re-saved since std.standard changed". This same project simulates fine in 2016.2 (without -93_mode, which is unsupported). I have created a new project in addition to upgrading the existing project, both with the same result. All VHDL files are of type VHDL (not VHDL 2008), and I tried 'set_param project.enableVHDL2008 0' to no avail. I found a couple of threads referencing the same error (here and here), but neither seems to solve my problem.
I would like to be able to use 2016.3 as it provides improvements that are helpful to me, but I can't if the simulator will not work. Help!
01-05-2017 10:38 AM
I have confirmed this problem also exists in the 2016.4 simulator. Both versions are installed on Ubuntu 16.04.1 LTS. Creating a new project with a single trivial file, adding the -93_mode flag to xsim.compile.xvhdl.more_options, and then trying to simulate results in an error.
Can someone from Xilinx please provide assistance?
Here are the test file contents and log.
entity test is
x : out std_logic
end entity test;
architecture std of test is
x <= '1';
end architecture std;
launch_simulation INFO: [SIM-utils-51] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'test' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/btrotter/workspace/vivado_test/2016.3/test.sim/sim_1/behav' xvhdl -m64 --relax -prj test_vhdl.prj -93_mode INFO: [VRFC 10-163] Analyzing VHDL file "/home/btrotter/workspace/vivado_test/2016.3/test.vhd" into library xil_defaultlib INFO: [VRFC 10-307] analyzing entity test INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/btrotter/workspace/vivado_test/2016.3/test.sim/sim_1/behav' Vivado Simulator 2016.3 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: /opt/Xilinx/Vivado/2016.3/bin/unwrapped/lnx64.o/xelab -wto e81b1fcb5f5b4e5a98436ddfbd9574d9 --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot test_behav xil_defaultlib.test -log elaborate.log Using 8 slave threads. ERROR: [VRFC 10-113] /home/btrotter/workspace/vivado_test/2016.3/test.sim/sim_1/behav/xsim.dir/xil_defaultlib/test.vdb needs to be re-saved since std.standard changed ERROR: [VRFC 10-147] xil_defaultlib.test failed to restore ERROR: [XSIM 43-3225] Cannot find design unit xil_defaultlib.test in library work located at xsim.dir/work. INFO: [USF-XSim-69] 'elaborate' step finished in '0' seconds INFO: [USF-XSim-99] Step results log file:'/home/btrotter/workspace/vivado_test/2016.3/test.sim/sim_1/behav/elaborate.log' ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/home/btrotter/workspace/vivado_test/2016.3/test.sim/sim_1/behav/elaborate.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
01-05-2017 04:23 PM
-93_mode should be passed to both xvhdl and xelab.
Please try to add -93_mode in xsim.elaborate.xelab.more_options field.
01-19-2017 02:02 PM
@graces: adding -93_mode to xsim.elaborate.xelab.more_options solved the original problem.
However, now I am trying to simulate a design using unisim.vcomponents and I get the following error:
ERROR: [VRFC 10-113] /opt/Xilinx/Vivado/2016.4/data/xsim/vhdl/unisim/unisim.vdbl needs to be re-saved since std.standard changed
How do I simulate using -93_mode and unisim? Please advise.
01-20-2017 10:53 PM
01-31-2017 09:51 AM
@svanapar, that is my suspicion. So the question is, is there a workaround? Per your request, here is a simple test case. Please advise.
library ieee; use ieee.std_logic_1164.all; library unisim; use unisim.vcomponents.all; entity unisim_test is port ( O : out std_logic; I : in std_logic ); end entity unisim_test; architecture std of unisim_test is begin INST : OBUF port map ( O => O, I => I ); end architecture std;
xvhdl -m64 --relax -prj unisim_test_vhdl.prj -93_mode ERROR: [VRFC 10-113] /opt/Xilinx/Vivado/2016.4/data/xsim/vhdl/unisim/unisim.vdbl needs to be re-saved since std.standard changed
02-04-2017 09:23 PM
I have reproduced the error, this seems like a bug. I will check this further and keep you updated.
ERROR: [VRFC 10-113] C:/Xilinx/Vivado/2016.3/data/xsim/vhdl/unisim/unisim.vdbl needs to be re-saved since std.standard changed
ERROR: [VRFC 10-147] unisim.vcomponents failed to restore
ERROR: [VRFC 10-149] 'vcomponents' is not compiled in library unisim [C:/Users/svanapar/Downloads/test.vhd:5]
03-10-2017 05:08 AM
04-20-2017 04:16 AM
02-26-2019 01:22 PM
03-06-2019 09:36 PM
Hi guys, I am not sure if I will be helpful, but I believe I found the same problem in the 2018.3 version. It synthesizes but does not simulate. My solution was to set the compilation order manually in order to avoid missing 'references'.