UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor ricaudjp
Visitor
6,582 Views
Registered: ‎11-04-2009

Problem with ARRAY and STD_LOGIC_VECTOR2

Hi,

 

I have a problem with an ARRAY which is transformed to STD_LOGIC_VECTOR2 by the simulator (ISim / ISE 12.2).

In my code I have defined :

 

 

type t_countOUT is array (0 to 1) of std_logic_vector (2 downto 0);

...

component top is
port (
pin_RESET : in std_logic;
pin_CLK_p : in std_logic;
pin_CLK_n : in std_logic;
pin_START : in std_logic;
pin_STOP : in std_logic;
pin_TEST : out std_logic_vector (2 downto 0);
pin_OUT : out t_countOUT;
pin_OUT2 : out std_logic_vector (31 downto 0)
);
end component top;

...

 

This works fine for synthesis and implementation. It also works for behavior simulation.

Even the "Post Place & Route Check Syntax" of ISim is OK, but the "Post Place & Route" simulation fails, with the error :

 

"Entity port pin_out does not match with type t_countout of component port"

 

Looking at the netgen generated by ISim, the ARRAY has been replaced by STD_LOGIC_VECTOR2 :

 

 

entity top is
port (
pin_STOP : in STD_LOGIC := 'X';
pin_START : in STD_LOGIC := 'X';
pin_globalRESET : in STD_LOGIC := 'X';
pin_CLK_n : in STD_LOGIC := 'X';
pin_CLK_p : in STD_LOGIC := 'X';
pin_OUT2 : out STD_LOGIC_VECTOR ( 31 downto 0 );
pin_OUT : out STD_LOGIC_VECTOR2 ( 1 downto 0 , 2 downto 0 );
pin_TEST : out STD_LOGIC_VECTOR ( 2 downto 0 )
);
end top;

 

I think this is the problem.

Is there something to do to keep the ARRAY declaration in the code, or have I missed something ?

 

Thank you

Regards

 

 

 

 

0 Kudos
7 Replies
Explorer
Explorer
6,564 Views
Registered: ‎09-11-2007

Re: Problem with ARRAY and STD_LOGIC_VECTOR2

Look for a check-box in the properties to have ISE generate only the architecture (not the entity) for the post-PAR simulation model..

 

Barry

0 Kudos
Visitor ricaudjp
Visitor
6,536 Views
Registered: ‎11-04-2009

Re: Problem with ARRAY and STD_LOGIC_VECTOR2

Thank you for your help, but checking this option brings others errors as entity "top" is no more compiled.

 

0 Kudos
Xilinx Employee
Xilinx Employee
6,526 Views
Registered: ‎09-14-2007

Re: Problem with ARRAY and STD_LOGIC_VECTOR2

Hi,

 

When you generate the architecture only, you will need to put the entity declaration in your Tb.

 

if you do this, then the issue will be resolved..

 

Thanks

Duth

 

0 Kudos
Visitor khawks
Visitor
5,726 Views
Registered: ‎06-13-2011

Re: Problem with ARRAY and STD_LOGIC_VECTOR2

Hi,

 

I have encounter the same problem, but i dont understand what do you mean by put the entity declaration in the TB. Do you mind to show me some example?

 

Thanks...

 

Khai

0 Kudos
Historian
Historian
5,709 Views
Registered: ‎02-25-2008

Re: Problem with ARRAY and STD_LOGIC_VECTOR2


@khawks wrote:

Hi,

 

I have encounter the same problem, but i dont understand what do you mean by put the entity declaration in the TB. Do you mind to show me some example?

 

Thanks...

 

Khai


You need to put your user-defined type into a package, and then use the package at the top of all source files that require that type.

----------------------------Yes, I do this for a living.
0 Kudos
Observer 07041978
Observer
1,119 Views
Registered: ‎01-24-2008

Re: Problem with ARRAY and STD_LOGIC_VECTOR2

Hi,

 

I have the same problem.

 

You need to put your user-defined type into a package, and then use the package at the top of all source files that require that type.

I tried, but I doesn't work. ****_par.prj file must be manually edited and package file added. After that std_logic_vector2 must be dealt with (isim sees array of std_logic_vector as std_logic_vector2). How?

0 Kudos
Visitor udayraj_mp
Visitor
214 Views
Registered: ‎07-28-2013

Re: Problem with ARRAY and STD_LOGIC_VECTOR2

Hi,

I am facing the same issue. If any solutions available for this issue, please share it. 

Regards

Udayraj MP

0 Kudos