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Visitor
Visitor
6,807 Views
Registered: ‎11-04-2009

Problem with ARRAY and STD_LOGIC_VECTOR2

Hi,

 

I have a problem with an ARRAY which is transformed to STD_LOGIC_VECTOR2 by the simulator (ISim / ISE 12.2).

In my code I have defined :

 

 

type t_countOUT is array (0 to 1) of std_logic_vector (2 downto 0);

...

component top is
port (
pin_RESET : in std_logic;
pin_CLK_p : in std_logic;
pin_CLK_n : in std_logic;
pin_START : in std_logic;
pin_STOP : in std_logic;
pin_TEST : out std_logic_vector (2 downto 0);
pin_OUT : out t_countOUT;
pin_OUT2 : out std_logic_vector (31 downto 0)
);
end component top;

...

 

This works fine for synthesis and implementation. It also works for behavior simulation.

Even the "Post Place & Route Check Syntax" of ISim is OK, but the "Post Place & Route" simulation fails, with the error :

 

"Entity port pin_out does not match with type t_countout of component port"

 

Looking at the netgen generated by ISim, the ARRAY has been replaced by STD_LOGIC_VECTOR2 :

 

 

entity top is
port (
pin_STOP : in STD_LOGIC := 'X';
pin_START : in STD_LOGIC := 'X';
pin_globalRESET : in STD_LOGIC := 'X';
pin_CLK_n : in STD_LOGIC := 'X';
pin_CLK_p : in STD_LOGIC := 'X';
pin_OUT2 : out STD_LOGIC_VECTOR ( 31 downto 0 );
pin_OUT : out STD_LOGIC_VECTOR2 ( 1 downto 0 , 2 downto 0 );
pin_TEST : out STD_LOGIC_VECTOR ( 2 downto 0 )
);
end top;

 

I think this is the problem.

Is there something to do to keep the ARRAY declaration in the code, or have I missed something ?

 

Thank you

Regards

 

 

 

 

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7 Replies
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Explorer
Explorer
6,789 Views
Registered: ‎09-11-2007

Look for a check-box in the properties to have ISE generate only the architecture (not the entity) for the post-PAR simulation model..

 

Barry

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Visitor
Visitor
6,761 Views
Registered: ‎11-04-2009

Thank you for your help, but checking this option brings others errors as entity "top" is no more compiled.

 

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Xilinx Employee
Xilinx Employee
6,751 Views
Registered: ‎09-14-2007

Hi,

 

When you generate the architecture only, you will need to put the entity declaration in your Tb.

 

if you do this, then the issue will be resolved..

 

Thanks

Duth

 

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Visitor
Visitor
5,951 Views
Registered: ‎06-13-2011

Hi,

 

I have encounter the same problem, but i dont understand what do you mean by put the entity declaration in the TB. Do you mind to show me some example?

 

Thanks...

 

Khai

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Historian
Historian
5,934 Views
Registered: ‎02-25-2008


@khawks wrote:

Hi,

 

I have encounter the same problem, but i dont understand what do you mean by put the entity declaration in the TB. Do you mind to show me some example?

 

Thanks...

 

Khai


You need to put your user-defined type into a package, and then use the package at the top of all source files that require that type.

----------------------------Yes, I do this for a living.
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Observer
Observer
1,344 Views
Registered: ‎01-24-2008

Hi,

 

I have the same problem.

 

You need to put your user-defined type into a package, and then use the package at the top of all source files that require that type.

I tried, but I doesn't work. ****_par.prj file must be manually edited and package file added. After that std_logic_vector2 must be dealt with (isim sees array of std_logic_vector as std_logic_vector2). How?

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Visitor
Visitor
439 Views
Registered: ‎07-28-2013

Hi,

I am facing the same issue. If any solutions available for this issue, please share it. 

Regards

Udayraj MP

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