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way2vipul
Visitor
Visitor
10,498 Views
Registered: ‎04-01-2014

Problem with JK-Flipflop simulation with isim

Hello dear,

 

I created a schematic diagram for JK flip flop shown below.

Schematic.png

 

 

 

then i made a test bench to test the JK flip flop. while i run the simulation it shows undefined q and Q0. 

 

 

 

schematic2.png

 

 

how to initialize the q and q0 i tryied following but did not get success still problem persist in the simulation please give me solution of this problem. 

 

 

 

Thank you

vipul

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7 Replies
gszakacs
Instructor
Instructor
10,488 Views
Registered: ‎08-14-2007

Your "JK flip-flop" has no reset signal.  So the value of Q and Q0 are unknown at startup.  The feedback in the flop is such that no amount of wiggling the inputs will get it to a known state from this condition.  You have two possible solutions:

 

1) add reset circuitry to the flop and drive the reset active at the start of simulation.

 

2) Use "force" to set the Q or Q0 output to a known state briefly after startup.

 

I'm attaching a Verilog test bench that illustrates solution 2.

-- Gabor
8,418 Views
Registered: ‎09-01-2015

hello, 

i tried Jk flip flop by drawing schematic . I have solved the problem of inital output but i am not getting proper output for input j=k=1 that is it should toggle for particular clock=1 but i am not geeting ans as shown, Plz help

 

I have converted it in T flip flop.

 

schematic.png
isim.png
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fredjobsearch
Visitor
Visitor
4,217 Views
Registered: ‎10-19-2012

I had the same problem. Finally getting around to making that gate level Apple II and couldn't find library of 74series parts. So have to make some.

 

 

Forcing didn't work for me on my JK flip flop which looked just like the one in the post.. Do you know why?? The clue is "DUMMY".

The schematic thing generates Verilog from the schematic. Those are in the ".vf" files. Some input and output can't be connected directly but require a wire be defined and it uses that. So internally the  Q  and Qnot or whatever signal he used are connected by the wire Q_DUMMY and Qnot_DUMMY. So forcing Q and Qnot only affects the output pins while forced but doesn't set Q_DUMMY and Qnot_DUMMY which remained "x" undefined.. So it doesn't work until forcing Q_DUMMY.

 

 

 

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ma97
Visitor
Visitor
3,372 Views
Registered: ‎04-01-2019

hi

I have the same problem

but i think this schematic that you draw is jk-latch; and you should follow as this pic

https://circuitdigest.com/electronic-circuits/jk-flip-flop-truth-table-working?destination=node/1424

D-flip-flop--with-NAND-gates-example.png

but this schematic dose not work in ise too;

there is my schematic with testbench;

PLz everyone can help and make it complete

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glszakacs
Newbie
Newbie
3,357 Views
Registered: ‎04-01-2019

The schematic you've posted is too simple to work as an edge-triggered device.  It would need a pulse (edge-detector) to source the clock signal.  Here's a master-slave flip-flop:

JK_master_slave.png

There is a description of its operation at:

https://www.electronics-tutorials.ws/sequential/seq_2.html

 

ma97
Visitor
Visitor
3,335 Views
Registered: ‎04-01-2019

very thanks; that's worked with master-slave (and added reset signal)

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glszakacs
Newbie
Newbie
3,325 Views
Registered: ‎04-01-2019

No problem.

By the way, I'm amazed at how much incorrect information I came accross looking for this schematic snippet.  The one from circuitdigest was just wrong - it should have NAND gates where it shows AND gates.  Even the master slave diagram I posted shows the clock as rising edge triggered, while the outputs actually toggle on the falling clock edge (the "master latch" toggles on the rising edge).  The clocks should be inverted to have rising edge outputs.  The lower NAND gates of each latch section can be increased to 3 inputs to add an active low reset signal.  Here's a Verilog description of the flip-flop with rising edge clock and active high reset:

`timescale 1ns / 1ps

`default_nettype none

module JK_ff
(
input wire j,
input wire k,
input wire clock,
input wire reset,
output wire Q,
output wire Q_not
);

wire j_NAND;
wire k_NAND;
wire slave_set_not;
wire slave_rst_not;
wire master_Q;
wire master_Q_not;

assign j_NAND = !(j & !clock & Q_not);
assign k_NAND = !(k & !clock & Q);
assign master_Q = !(j_NAND & master_Q_not);
assign master_Q_not = !(k_NAND & master_Q & !reset);
assign slave_set_not = !(master_Q & clock);
assign slave_rst_not = !(master_Q_not & clock);
assign Q = !(slave_set_not & Q_not);
assign Q_not = !(slave_rst_not & Q & !reset);

endmodule

`default_nettype wire

 

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