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Participant indra_v5
Participant
8,196 Views
Registered: ‎02-06-2015

Problem with looping!!

  HI, I have a small problem,please help me out,I have instantiated 4 modules i.e A,B,C,D in a separate module called "Top Module" such that each module works with the signals from the preceding modules i.e A>B>C>D , each module does some computations,now I want the modules to run in a recursive type of a way ie the output signal from module D will be given as input signal to module A,this looping type of behavior will happen until a condition is satisfied  and the final output will be taken from A,so how to go about this? 

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3 Replies
Scholar markcurry
Scholar
8,165 Views
Registered: ‎09-16-2009

Re: Problem with looping!!

 

Sounds like you need a state machine.

 

Blocks "A,B,C,D" are sequential right?  Or are they purely combinatorial?  Can you register between blocks/endpoints?

 

More details would help.

 

Regards,

 

Mark

 

 

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Moderator
Moderator
7,478 Views
Registered: ‎07-01-2015

Re: Problem with looping!!

Hi @indra_v5;

 

You can try using multiple process blocks to define the i/p and o/p signals of the modules and status signal of each process block will help in monitoring the data flow.

 

Please give detailed information regrding your query.

 

Thanks 

Arpan

Thanks,
Arpan
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Historian
Historian
7,441 Views
Registered: ‎01-23-2009

Re: Problem with looping!!

From the way you are describing it, I suspect that you are thinking "algorithmically" - like you would when writing software.

 

When you are using hardware, you have to think like hardware. You have to figure out what the architecture of your system is going to be. If there is some kind of iterative process that will continue operating until "it is done", then you need to code the control mechanism of this; you will need to determine what will be done during each clock, what criteria is used to determine when to stop processing and what signalling protocol you will use to indicate that a final result is available. You need to determine if you the number of clocks (worst case) to get your result satisfies your system requirements, and, if not, determine how to exploit paralleism.

 

If you are considering trying something like this without a clock, DON'T! While theoretically possible to create some kind of asynchronous systolic array that "settles" to a solution, this should not be done - particularly not in an FPGA and certainly not using the normal FPGA tools. Synthesis will have no idea how to optimize something like this, and static timing will go nuts. You will be completely at the mercy of the nature of the LUTs in terms of whether or not this thing will settle properly or oscillate due to glitching behaviour. The performance of the system will be all over the map and highly dependent on place and route, and it will be virtually impossible to interface something like this with "normal" logic...

 

Avrum

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