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Newbie paolosofia
Newbie
1,082 Views
Registered: ‎02-08-2018

Problem with post-PAR simulation 4bit counter

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Hi, my friends and I are doing a project for an exam at university. This is our first time working with xilinx. We are trying to implement a 4 bit counter with some the options to go up and down, load a number,stop the count, with an asynchronous reset. It all works fine with the behavioural sim, but when we try to do the PAR simulation, the are two problems.1 In some cases the output changes when the clock is at 0 and 2. there is an hazard of about 9 ps almost every time the output changes. Why? What do we do wrong? here's the code and sorry for my english

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

entity esame2 is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
start_stop : in STD_LOGIC;
up_down : in STD_LOGIC;
value : in STD_LOGIC_VECTOR (3 downto 0);
insert : in STD_LOGIC;
num : out STD_LOGIC_VECTOR (3 downto 0));
end esame2;

architecture RTL of esame2 is
signal vet : STD_LOGIC_VECTOR (3 downto 0);
begin
process(reset, clock)
begin
if reset = '1' then
vet <= vet - vet;
elsif (clock'event and clock = '1') then
if(start_stop = '0') then
vet <= vet;
elsif(insert = '1') then
vet <= value;
elsif(up_down = '1')then
if(vet = "1111") then
vet <= "0000";
else vet <= vet + 1;
end if;
elsif(up_down = '0')then
if(vet = "0000") then
vet <= "1111";
else vet <= vet - 1;
end if;
else vet <= vet;
end if;
else vet <= vet;
end if;
end process;
num <= vet;

end RTL;

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Scholar richardhead
Scholar
1,550 Views
Registered: ‎08-01-2012

Re: Problem with post-PAR simulation 4bit counter

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In a real circuit, each bit is on a separate path. And each path will have a different delay. What you are seeing is bit 0 changing faster than bit 1. This is fairly normal. As you point out, this is only a 9ps hazard, and so well within the setup/hold timing required for the circuit.

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Scholar richardhead
Scholar
1,551 Views
Registered: ‎08-01-2012

Re: Problem with post-PAR simulation 4bit counter

Jump to solution

In a real circuit, each bit is on a separate path. And each path will have a different delay. What you are seeing is bit 0 changing faster than bit 1. This is fairly normal. As you point out, this is only a 9ps hazard, and so well within the setup/hold timing required for the circuit.

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Newbie paolosofia
Newbie
1,040 Views
Registered: ‎02-08-2018

Re: Problem with post-PAR simulation 4bit counter

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thank you very much for the help. I thought about the fact that a 9 ps hazard is not a problem for the circuit but I wasn't sure, so I asked. Thank you again

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Moderator
Moderator
1,030 Views
Registered: ‎09-15-2016

Re: Problem with post-PAR simulation 4bit counter

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Hi @paolosofia,

 

If your query is addressed then can you please close this thread by marking the post which helped as "Accept as solution".

 

 

Thanks & Regards,
Sravanthi B

Thanks & Regards,
Sravanthi B
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