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Adventurer
Adventurer
6,369 Views
Registered: ‎08-24-2008

Problem with timing simulation

Hi,

 

 I have a design that was successfully placed and routed for the specified clock period constraint. So, there was no timing violation reported during implementation. However, when I do the post route simulation in Isim, it reports timing violations in certain parts of the design. I find it very strange. I am using the default simulator time resolution of 1ps and my clock period is 10 ns. I can see the clock and the outputs in timing simulation. Some output values are correct while others are wrong and Isim reports set up violations.

 

Any comment would be appreciated!

 

Thanks!

Sharad

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3 Replies
Contributor
Contributor
6,365 Views
Registered: ‎09-12-2013

Re: Problem with timing simulation

Hi Sharad,

Could you please attach the timing report(.twx) file here so that we can check whether there is any issue or not?

Please post the timing violations which tool is reporting so that it will be easy to comment.

If possible please try with the latest version of ISE i.e. 14.7

Cheers,
Jaime
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Community Manager
Community Manager
6,346 Views
Registered: ‎07-23-2012

Re: Problem with timing simulation

Hi Sharad,

This thread is a good read- http://forums.xilinx.com/t5/Timing-Analysis/About-Timing-errors-in-Post-route-simulation-in-modelsim/td-p/65363

Are there any unconstrained paths in your design? Are you 100% sure that there are no timing violations in your design.

Please share the isim.log file.

Regards,
Krishna
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Adventurer
Adventurer
6,330 Views
Registered: ‎08-24-2008

Re: Problem with timing simulation

Hi Jaime and Krishna,

 

I have attached the Post-PAR timing report file, the ISim log file, the RTL source code as well as the TCL script I run in Isim.

 

I am using ISE 14.7 and ISim.  I have generated all the floating point cores from within ISE.

 

I have only one constraint related to the clock period in my design and am not usign any OFFSET IN or OFFSET OUT constraint because this design(module) is part of another design. I have enabled reporting of uncontrained paths (set -u to 100 in Implementation options) in the timing report which obviously reports unconstrained paths due to lack of OFFSET IN constraint.  I just wanted to ensure that this module worked at my desired clock frequency (100 MHz) and it has worked this way with my previous modules.

 

I have noticed that MAP removes my 3 top level ports: a<31>, b<31>, c<31> and I am at my wits' end trying to figure out why they are being removed. From the RTL it is clear that they are not loadless. They are not sourceless either. They are inputs to different single precision floating point multipliers. I have attached my RTL source code also. I have digged into the map report to see the reasons for their removal, but I am unable to find any useful info.

 

I also tried post translate (works fine) and post map simulations (throws up set up violations).

 

I also get the warning about illegal redeclaration of glbl ( it is there in glbl.v as well as the single precision FP adder core.).

 

You can see from the map report as well as the reported timing violations (post route)  that they are all related to the FP cores.

 

The  zipped fiolder has following files:

1. function_hardware_memoization.v   --- RTL source

2. function_hardware_memoization.twx    -- Timing Report

3. function_hardware_memoization_map.mrp  -- Map report

4. simulation_function_hw_mem.tcl   -- TCL file for simulation

5. isim.log

 

Regards,

Sharad

 

 

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