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aylon_porat
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Registered: ‎03-11-2021

QDMA subsystem for pcie streaming example design tests failing with modelsim

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Hello,

I am trying to simulate, using modelsim, the example design for the QDMA subsystem for pcie v4 using the `AXI Stream with Completion` option under the `DMA interface` field (test name is `qdma_st_test0`) however the test fails. using xsim, the test passes (after applying patch AR 75598 rev 1), but using modelsim, the h2c streaming data received at the user logic is incorrect & has seemingly random extra 0 bytes ( see waveforms below for an example )

h2c streaming data received with modelsim:

h2c streaming modelsim data.png

h2c streaming data received with xsim:

aylon_porat_0-1615493366220.png

 

I am using Vivado 2020.1 with the patch AR 75598 (AR# 75598: Queue DMA subsystem for PCI Express 4.0 (Vivado 2020.1) - Tactical Patch for Issue Fixes (xilinx.com)) rev 1 and Modelsim DE 2020.2 (32 bit)

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bandi
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Registered: ‎09-15-2016

HI @aylon_porat ,

As from the below user guide ug973 page#12:

https://www.xilinx.com/content/dam/xilinx/support/documentation/sw_manuals/xilinx2020_2/ug973-vivado-release-notes-install-license.pdf

ModelSim PE/DE 32-bit support has been discontinued since Vivado 2020.1 release. Hence, can you please try using Modelsim SE 64bit version (2020.2) and check if you are still facing issues.

Thanks & Regards,
Sravanthi B
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bandi
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409 Views
Registered: ‎09-15-2016

HI @aylon_porat ,

As from the below user guide ug973 page#12:

https://www.xilinx.com/content/dam/xilinx/support/documentation/sw_manuals/xilinx2020_2/ug973-vivado-release-notes-install-license.pdf

ModelSim PE/DE 32-bit support has been discontinued since Vivado 2020.1 release. Hence, can you please try using Modelsim SE 64bit version (2020.2) and check if you are still facing issues.

Thanks & Regards,
Sravanthi B
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