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d_shi
Newbie
Newbie
509 Views
Registered: ‎11-17-2020

Question mark in Vivado simulator

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Hello,

In Vivado simulator behavioural simulation I see signals appearing as question marks when examining the waveforms.

I assign the signals synchronously in a process, as such,

                v_data_sequence <= (0 => (12 => '1', 11 => '1', 1 => '1', others => '0'),
                                    1 => (10 => '1', 9 downto 0 => i_digipot_1_setting, others => '0'),
                                    2 => (12 => '1', 11 => '1', 1 => '1', others => '0'),
                                    3 => (10 => '1', 9 downto 0 => i_digipot_2_setting, others => '0'),
                                    4 => (8 => '1', others => '0'),
                                    5 => (14 => '1', 13 downto 0 => i_DDS_setting(13 downto 0), others => '0'),
                                    6 => (12 => '1', 8 => '1', others => '0'),
                                    7 => (14 => '1', 13 downto 0 => i_DDS_setting(27 downto 14), others => '0'),
                                    8 => (15 => '1', 14 => '1', others => '0'),
                                    9 => (others => '0'));

 and v_data_sequence is instantiated

type data_array is array (natural range <>) of std_logic_vector(15 downto 0);
signal v_data_sequence : data_array(6 + 2 + 2 - 1 downto 0);

? is not a std_logic value so I'm not clear on the meaning here.

The testbench and DUT are both VHDL-2008.

Can someone point me to the problem or the lines in the Vivado Simulator documentation? Thanks.

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d_shi
Newbie
Newbie
493 Views
Registered: ‎11-17-2020

Hi Richard,

Yes, the bits are all marked in this way.

I found the problem. It appears that this VHDL-2008 feature is not supported by Vivado simulator, and as a result, it places these question marks. I was able to resolve the issue like this:

                v_data_sequence(0) <= (12 => '1', 11 => '1', 1 => '1', others => '0');
                v_data_sequence(1) <= "000001" & i_digipot_1_setting;
                v_data_sequence(2) <= (12 => '1', 11 => '1', 1 => '1', others => '0');
                v_data_sequence(3) <= "000001" & i_digipot_2_setting;
                v_data_sequence(4) <= (8 => '1', others => '0');
                v_data_sequence(5) <= "01" & i_DDS_setting(13 downto 0);
                v_data_sequence(6) <= (12 => '1', 8 => '1', others => '0');
                v_data_sequence(7) <= "01" & i_DDS_setting(27 downto 14);
                v_data_sequence(8) <= (15 => '1', 14 => '1', others => '0');
                v_data_sequence(9) <= (others => '0');
--                v_data_sequence <= (0 => (12 => '1', 11 => '1', 1 => '1', others => '0'),
--                                    1 => (10 => '1', 9 downto 0 => i_digipot_1_setting, others => '0'),
--                                    2 => (12 => '1', 11 => '1', 1 => '1', others => '0'),
--                                    3 => (10 => '1', 9 downto 0 => i_digipot_2_setting, others => '0'),
--                                    4 => (8 => '1', others => '0'),
--                                    5 => (14 => '1', 13 downto 0 => i_DDS_setting(13 downto 0), others => '0'),
--                                    6 => (12 => '1', 8 => '1', others => '0'),
--                                    7 => (14 => '1', 13 downto 0 => i_DDS_setting(27 downto 14), others => '0'),
--                                    8 => (15 => '1', 14 => '1', others => '0'),
--                                    9 => (others => '0'));

 

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richardhead
Scholar
Scholar
502 Views
Registered: ‎08-01-2012

These values are being displayed as hex. If there are X or U values in the array, especially if its mixed, it will display ?

Try displaying the value as binary, or expand the bits in the waveform to see what they all are.

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d_shi
Newbie
Newbie
494 Views
Registered: ‎11-17-2020

Hi Richard,

Yes, the bits are all marked in this way.

I found the problem. It appears that this VHDL-2008 feature is not supported by Vivado simulator, and as a result, it places these question marks. I was able to resolve the issue like this:

                v_data_sequence(0) <= (12 => '1', 11 => '1', 1 => '1', others => '0');
                v_data_sequence(1) <= "000001" & i_digipot_1_setting;
                v_data_sequence(2) <= (12 => '1', 11 => '1', 1 => '1', others => '0');
                v_data_sequence(3) <= "000001" & i_digipot_2_setting;
                v_data_sequence(4) <= (8 => '1', others => '0');
                v_data_sequence(5) <= "01" & i_DDS_setting(13 downto 0);
                v_data_sequence(6) <= (12 => '1', 8 => '1', others => '0');
                v_data_sequence(7) <= "01" & i_DDS_setting(27 downto 14);
                v_data_sequence(8) <= (15 => '1', 14 => '1', others => '0');
                v_data_sequence(9) <= (others => '0');
--                v_data_sequence <= (0 => (12 => '1', 11 => '1', 1 => '1', others => '0'),
--                                    1 => (10 => '1', 9 downto 0 => i_digipot_1_setting, others => '0'),
--                                    2 => (12 => '1', 11 => '1', 1 => '1', others => '0'),
--                                    3 => (10 => '1', 9 downto 0 => i_digipot_2_setting, others => '0'),
--                                    4 => (8 => '1', others => '0'),
--                                    5 => (14 => '1', 13 downto 0 => i_DDS_setting(13 downto 0), others => '0'),
--                                    6 => (12 => '1', 8 => '1', others => '0'),
--                                    7 => (14 => '1', 13 downto 0 => i_DDS_setting(27 downto 14), others => '0'),
--                                    8 => (15 => '1', 14 => '1', others => '0'),
--                                    9 => (others => '0'));

 

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