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Observer
Observer
5,265 Views
Registered: ‎11-23-2010

Questions regarding post PAR simulation ...

Hi,

I was trying out post place and route sim. on a very simple FSM design. The FSM goes through a couple of states, does a multiplication, and then, gives a done signal.

 

Behaviorial sim is fine. But when I run post PAR sim (in modelsim), the signals are not asserting at the rising edge of the clock, but about 8ns after that. I looked around on the forums and it said that the design needs to be constrained. So in the UCF file, I constrained the clk to 50ns period, (and I run my sim at 50ns period as well). I also put in offset in and offset out constraints and there are no timing violations. Timing report is clean. However, even with that, the signals donot assert at the rising edge of the clock.

 

So, I was wondeing if someone could help answer these questions -

 

1) I can understand that the top level o/p signals have a delay because of pad, o/p buffers etc. But why does an internal signal, like trig_out (as seen in the screenshot) also have a delay and does not assert on the rising_edge of the clk?

 

2) Since the design is fully constrained, can I do anything else to get the signals to happen at the rising edge of the clock? Or such offsets are expected in post PAR sim?

 

3) Even though I specify OFFSET = OUT 15 ns AFTER CLK; the o/p signals still assert 8.56 ns after the rising edge of the clock. The min. allowable offset out in the timing report is 8.2 ns. So if I specify a larger offset out than 8.2, why do I still see the offset on the o/p signals as 8.56ns and not 15 ns?

 

4) I try to see some internal signals but they get removed, even when I use the keep constraint or even when I uncheck "remove eq register" from synth and implement properties. So is there any other way I can keep the internal signal and view it in the sim?

 

5) Since this is a vey small/basic module that I am trying to do timing sims for, is it that ISE spreads the logic over all the chip and so the delays get bigger because of the longer paths? If so, how can I constraint the area of my design and how can I know what the min area or region in which to constraint the design to?

 

I've been trying to get answers to the above for a while. so it would be great if someone can point out what I'm missing out on ... :)

 

thanks and regards,

Z

sc_post_par_sim.JPG
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Professor
Professor
5,262 Views
Registered: ‎08-14-2007

 

 

1) I can understand that the top level o/p signals have a delay because of pad, o/p buffers etc. But why does an internal signal, like trig_out (as seen in the screenshot) also have a delay and does not assert on the rising_edge of the clk?

 

Even internal flops have some delay, and the simulation will show routing delays as well.  Do you know of any

physical flip-flops that have zero delay from clock to Q?

 

2) Since the design is fully constrained, can I do anything else to get the signals to happen at the rising edge of the clock? Or such offsets are expected in post PAR sim?

 

No and Yes, respectively.

 

3) Even though I specify OFFSET = OUT 15 ns AFTER CLK; the o/p signals still assert 8.56 ns after the rising edge of the clock. The min. allowable offset out in the timing report is 8.2 ns. So if I specify a larger offset out than 8.2, why do I still see the offset on the o/p signals as 8.56ns and not 15 ns?

 

OFFSET OUT constrains the maximum allowable time from the input clock to the output pin.  The post P&R simulation does not use the constraint values, it uses the actual (maximum) delay values calculated from the placement.  So if your design meets constraints, the clock to output delay should be less than 15 ns.

 

4) I try to see some internal signals but they get removed, even when I use the keep constraint or even when I uncheck "remove eq register" from synth and implement properties. So is there any other way I can keep the internal signal and view it in the sim?

 

The KEEP constraint only ensures that the signal is kept through synthesis.  The map phase can remove signals that don't affect any outputs of the design.  You should apply an "S" constraint if you want the signal "saved" after map.  Also note that some signal names may change during netlist generation.  For example if you have multiple levels of hirarchy that use the same signal, it would have a different name at each level of the hierarchy.  However the netlist will only keep one of the names for the signal, because it represents only a single node in the netlist.

 

5) Since this is a vey small/basic module that I am trying to do timing sims for, is it that ISE spreads the logic over all the chip and so the delays get bigger because of the longer paths? If so, how can I constraint the area of my design and how can I know what the min area or region in which to constraint the design to?

 

Generally speaking, as long as your design meets the timing constraints you give it, the placer will not try to pack the design any further.  You can try to overconstrain the design, for example setting the PERIOD constraint on your clock to 20 ns instead of 50.

 

Just a comment:

 

In a synchronous system, as long as a signal meets the setup time to the next clock edge you should have

no issues with functionality of the design.  Is there some reason why you want the signals to change as

quickly as possible after a clock edge (other than the output pins)?  I would think that meeting the PERIOD

constraint should be good enough.

 

-- Gabor

 

 

 

-- Gabor
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Observer
Observer
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Registered: ‎11-23-2010

Hi Gabor,

Thanks a ton for your reply!!! really appreciate it because I had been struggling with these aspects for some time.

 

1) Yes, no FF will have a 0 clk to q delay. so that would explain why internal signals also have some delay before asserting.

 

2) So I assume there is no way of making signals happen at the rising edge in post PAR sims. because of routing delays etc.

 

4) will try the "s" constraint

 

5) I did try overconstraining the design by putting a clk period of 20 ... but the timing failed as the min. allowable period was 24.897 ns ... hence the UCF constraint of 50ns

 

as for 3) and why i'm trying to get the signals to happen as close to rising edge as possible - i was thinking about hold time - suppose my o/p signal needs to go into a chip which samples the o/p line at every rising edge of the clk. now as per the post par sims, the o/p line asserts 8.56 ns after the rising edge of the clk. suppose the chip has a hold time window of 9 ns ... so in this case, my o/p would be asserting within the hold time window and so this would lead to a metastability condition. so my 2 options are - (A)bring the signal assertion to as close to the rising edge as possible. OR (B)push it out with a larger OFFSET OUT AFTER constraint so that at least the signal does not transition inside the hold window. Now since you pointed out that (A) cannot happen because there will always be routing, clk-to-q delays, so the other option is doing (B). so i was trying to come up with some way that would take the signal transition out of the hold window and at the next rising edge, the other chip gets the proper value ... can you suggest a way of doing this?

 

Thanks in advance for your reply...

Z.

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