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Observer asanghi
Observer
246 Views
Registered: ‎01-11-2019

RTL include file ERROR

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I am putting some of the macros in a file and including this file in every file, where these macros are needed. However, when I compile for simulation, I get the following message.

ERROR: [Common 17-49] Internal Data Exception: HDDASrcFileProxy::HDDASrcFileProxy: Given HDDASrcFile isn't associated with a fileset. File: '/home/asanghi/project/valtix-hw/decompression/design/rtl/macros.v'

What is causing this error.

Thanks

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Xilinx Employee
Xilinx Employee
165 Views
Registered: ‎07-16-2008

回复: RTL include file ERROR

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If the include file has already been added to the project, please change its file type to Verilog Header.

set_inc_header.png

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3 Replies
Xilinx Employee
Xilinx Employee
210 Views
Registered: ‎07-16-2008

回复: RTL include file ERROR

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It looks you launched the simulation from Vivado GUI.

Check the Sources window, is the include file seen under the Verilog Header directory? Following is an example figure.

src_inc.png

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Observer asanghi
Observer
185 Views
Registered: ‎01-11-2019

回复: RTL include file ERROR

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Thank you for your response. No. the include file does not show up there. Also, the Sources window status is stuck in "Updating" mode with circular arrow rotating forever.

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Xilinx Employee
Xilinx Employee
166 Views
Registered: ‎07-16-2008

回复: RTL include file ERROR

Jump to solution

If the include file has already been added to the project, please change its file type to Verilog Header.

set_inc_header.png

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------