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Contributor
Contributor
8,728 Views
Registered: ‎04-22-2014

RTL synthesis problem

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HI All,

 

My name is Dasarath.

 

I am simulating the SATA with xilinx GTX ( virtex 6).

So i gave the unisims, unimacro,xilinxcorelib and secureip files as library files for compilation.

At simulation phase getting following error

 

ncsim: *E, ERRIPR error within protected source code.

 

 

In simulation doucment suggested that to use secureip libraries with IUS, an export control regulation license is required.

 

The above mentioned error becasue of this license or anything i am missing to provide to simulation tool.


regards

P Dasarath

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1 Solution

Accepted Solutions
Moderator
Moderator
13,403 Views
Registered: ‎04-17-2011

Re: RTL synthesis problem

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There was some issue in 13.x ISE with NCSIM. 

I would suggest you to use 14.x version of tool.

 

There seems to be some libraries in the NCSIM secureip set which is causing this issue.

Try to use only GTEX1 library :

$XILINX/secureip/ncsim/gtxe1_ncsim/gtxe1_cell.list.f  

 

How to do this?

Refer to single step process in http://www.xilinx.com/support/answers/31060.htm

Replace -f $XILINX/secureip/ncsim/ncsim_secureip_cell.list.f \

with

-f $XILINX/secureip/ncsim/gtxe1_ncsim/gtxe1_cell.list.f  \ (as you are using only GTX) and try.

Regards,
Debraj
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6 Replies
Moderator
Moderator
8,725 Views
Registered: ‎01-16-2013

Re: RTL synthesis problem

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Hello,

Which NCSIM version you are using?
XILINX library of which version?

Thanks,
Yash
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Contributor
Contributor
8,710 Views
Registered: ‎04-22-2014

Re: RTL synthesis problem

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Cadence Simulation tool is INCISIV 12.07.007

and Xilinx ISE 31.1

 

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Moderator
Moderator
8,705 Views
Registered: ‎01-16-2013

Re: RTL synthesis problem

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Hello,

This is ncsim issue. please try using 12.20 or later version of tool.

or you can try using irun command.
for example refer below command:


irun \
+TESTNAME=sample_smoke_test0 \
-define NCV \
-define SIMULATION \
-define DISABLE_COLLISION_CHECK \
-timescale 1ns/1ps \
-access +rwc \
-incdir ../ \
-incdir ../../source \
-incdir ../../example_design \
-incdir ../tests \
-incdir ../dsport \
-k /dev/null \
+libext+.v+ \
-y $XILINX/verilog/src/simprims \
-y $XILINX/verilog/src/unisims \
-f $XILINX/secureip/ncsim/ncsim_secureip_cell.list.f \
$XILINX/verilog/src/glbl.v \
-file board_v.f \
${XILINX}/verilog/src/unisims/PCIE_2_0.v \
${XILINX}/verilog/src/unisims/GTXE1.v

FYI.. You have to modify this command according to your requirement.

Thanks,
Yash

Contributor
Contributor
8,676 Views
Registered: ‎04-22-2014

Re: RTL synthesis problem

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Hi Yash,

 

Thanks for your response.

 

Even with Second options, getting the same error and i am unable to proceed.

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Xilinx Employee
Xilinx Employee
8,670 Views
Registered: ‎07-16-2008

Re: RTL synthesis problem

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The error should be related to compiling secureip sources.

Do you have an export control regulation license for IUS as documented in sim.pdf?

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Don't forget to reply, kudo, and accept as solution.
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Moderator
Moderator
13,404 Views
Registered: ‎04-17-2011

Re: RTL synthesis problem

Jump to solution

There was some issue in 13.x ISE with NCSIM. 

I would suggest you to use 14.x version of tool.

 

There seems to be some libraries in the NCSIM secureip set which is causing this issue.

Try to use only GTEX1 library :

$XILINX/secureip/ncsim/gtxe1_ncsim/gtxe1_cell.list.f  

 

How to do this?

Refer to single step process in http://www.xilinx.com/support/answers/31060.htm

Replace -f $XILINX/secureip/ncsim/ncsim_secureip_cell.list.f \

with

-f $XILINX/secureip/ncsim/gtxe1_ncsim/gtxe1_cell.list.f  \ (as you are using only GTX) and try.

Regards,
Debraj
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
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