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Registered: ‎01-27-2008

Re: Problem with module and test bench

@ejleiss  (tagged as Xilinx moved thread, but not the whole thread, @hj )

The signals in the module are ultimately what matter.

I haven't coded in VHDL for about 4 years but if you want the state_SM_main, r_num_bits, r_data_bits at the top level you want to set them as monitors of the dut.state_SM_main, dut.r_num_bits ... signals. It's a lot easier in SystemVerilog but I think VHDL 2008 integrated hierarchical monitoring, which is what you want to do - monitor the signals in your unit under test.

The top level signals (bolded above) connect to nothing but state_SM_main is initialized, which is the confusion. You'll note that r_num_bits and r_data_bits are probably U.

Your testbench is working for the UUT - the signals you want to drive are driving and causing transitions in dut.state_SM_main.

Original thread before this post was moved:

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