We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Visitor wuzidege
Registered: ‎04-18-2012

Re: Zero Defect Mindset

simultion of Multiply Accumulator

When I use the Multiply Accumulator IP Core simulation ,its configuration as:

input port A and B are set :14 bit ,signed. and the mac counter is set 200,clock rate is 50Mhz,result width is set 36bit.and assert the Reset  CE signals.

I simply instantiation the core.the ISE project as follows:

module demo(clk










input clk;

input [13:0] A,B;


input RST;

input FD,ND;

input CE;

output RDY;

output [35:0] Q;


sine_macc inst_macc(










   ); // synthesis black_box




The simultaion result is strang,not like the datasheet that.

Input port A and B are set “00000000000001”in testbench,form the figure ,we can see that When CE is valid,Q is changed at the rising edge of clk,but the ND and FD is set zero.why the Q output port is changed?





0 Kudos