I try to create a ring buffer using a Simple Dual Port RAM. I'm feeding both ADDR Pins with the same Addresses and the Clock at ClkA and ClkB is synchronous as well. I Would expect a delay of the full length of the RAM. In my case 1024. But I get only one clock delay caused by the output register of the RAM. In addition I get Warnings like that:
Instance /top_tb/UUT/DualPortRAM_1/U0/ : Warning: blk_mem_gen_v2_8 WARNING: collision detected: A write address: 0000000000, B write address: 0000000000
I proofed that the read first mode is set in the VHDL-Modell. Do I have to set something else to get this work?