hi,
i was doing a post route timing simulation with modelsim (xilinx ise 10.1), for the first time ... the design is simple - an FSM with some states, signal mult_start is supposed to assert/deassert and then done is supposed to assert. behaviorial simulation is fine and the signals assert/deassert at the rising edge of the clock. but in timing simulation, i noticed that mult_start and done were asserting about 1.2 ns before the rising edge of the clock! (screenshot attached)
I know this is timing simulation so the tool accounts for the path delays etc. but signals asserting 1.2 ns before the clk edge, is that normal? because traditionally the signals assert at the rising edge of the clock in the FSM. and if this is normal, do i need to account for this 1.2 ns shift by doing something? or is it normal?
