09-21-2018 10:58 AM
I just installed the BITVis UVVM testbench packages for simulating an axilite master core in my Ultrascale design, and found that Vivado 2018.2 still lacks essential VHDL2008 language support.
ERROR: [XSIM 43-4187] File "D:/test_ip/test_axi_lite_master_1.0/src/types_pkg.vhd" Line 39 : The "Vhdl 2008 Unconstrained Array Type as Subtype in Array Type Definition" is not supported yet for simulation.
This problem, along with the lack of support for VHDL2008 Contexts, is very annoying. Please upgrade the priority of this language feature for Vivado.
REQUEST FOR OTHER VHDL USERS: Please append your vote of support to this thread if you need this language upgrade in Vivado.
09-22-2018 12:21 AM
I support this.
Although if all it is doing is pushing users to 3rd party sim tools, I dont really see a business case for Xilinx.
09-23-2018 12:02 PM
I support this - and the need to make Vivado simulation better support all versions of VHDL.
For example, Vivado 2018.2 seems unable to do post implementation timing simulation (see <this> post) - even with older versions of VHDL.
09-25-2018 04:58 AM
As per UG900 Post Synthesis and Post Implementation timing simulations are not supported for VHDL
09-25-2018 05:17 AM - edited 09-25-2018 05:33 AM
....timing simulations are not supported for VHDL
That's actually part of our overall complaint. Why doesn't VHDL get equal footing with Verilog?
However, I did not write my original complaint clearly - sorry.
Yes, I do use VHDL. However, as @graces explained to me "You can have a pure VHDL RTL design but write out a Verilog simulation netlist (write_verilog) from synthesized or implemented design. That netlist still allows you to perform timing simulation." As shown in the post that I referenced, using write_verilog this way did not result in correct results for post-implementation timing simulation.
It is still unclear to me whether this is a problem with post implementation timing simulation in general or whether it is a using-VHDL problem.
09-26-2018 01:13 AM
If you have a sample project that shows incorrect results / results different to another third party simulator and are willing to share it then let me know and I can send you an EzMove link to transfer the files securely.
If I can replicate the issue then I will be happy to file a Change Request to have the issue investigated and fixed.
Support for VHDL Timing simulations in Vivado Simulator are not likely to be included in the near future.
It is my understanding that full coverage for SystemVerilog and VHDL-2008 in synthesis currently has higher priority.
09-26-2018 04:51 AM - edited 09-26-2018 04:53 AM
The following post has a lengthy discussion with @graces about my problem with post-impl timing simulation. Message 16 in that post summarizes the problem and contains my archived project from Vivado v2018.2.
Thank you for help with my problem and for letting us know that we can expect improved support for VHDL-2008.
09-27-2018 12:59 AM
I retrieved the project that you uploaded, implemented it and ran post implementation timing simulations in both Vivado Xsim 2018.2 and ModelSim 10.6c and the results were identical.
Let me know if I should have tried something different?
09-27-2018 06:24 AM
Thank you for continued help!
I did not compare results from ModelSim and Vivado for Post-Implementation Timing Simulation (PITS). However, results from Vivado PITS and Vivado Post-Implementation Function Simulation (PIFS) were found to be identical - which is an indicator of the problem.
Specifically, please consider the circuit shown below whose behavior I am simulating. In short, after the asynchronous clear, CLR1, for register, REG1, goes low then the output of REG1 (and output, OUT1) should go high “shortly after” the next rising edge of CLK1.
However, PITS and PIFS both show that OUT1 goes high on (and not “shortly after”) the rising edge of CLK1. For Kintex-7, I estimate “shortly after” to be the sum of delays through IBUF (~1ns), BUFR (~1ns), FDCE (~0.5ns), and OBUF(~2ns) – or about 4.5ns in total.
Since PITS shows that OUT1 goes high simultaneously with the rising edge of CLK1 (and not ~4.5ns after rising edge of CLK1) then I believe that PITS is not working properly (or I am not using PITS properly).
10-01-2018 02:09 PM
I ran across this thread after encountering an almost identical issue, wherein Vhdl2008 unconstrained record types are unsupported in simulation. This was a pretty simple piece of code, where I'm creating an AXI-Stream type and I don't want a bunch of types; one for 32 bits of tdata, 16 bits of tuser; another for 24 bits of tdata, 16 bits of tuser; and on an on ad infinity.
If the naming is accurate, VHDL-2008 is 10 years old now. Xilinx at least let us know what we can expect when. Will VHDL-2008 be supported in vivado simulator by 2020? 2025?
10-03-2018 04:00 AM
I fully support the request. This feature is absolutely fundamental in order to develop clean, portable code. Because of ths very issue alone my whole company has to use ModelSim for behavioural simulation, with considerable additional cost.
Vivado simulator is great and, for the rest, we are very happy with it, but please add this feature as soon as possible, it is making our life really hard.
10-03-2018 06:39 AM
Btw - to highlight how far behind Xilinx are:
VHDL 2018 is about to be, or has just been released - and Aldec are demoing some feature support in their beta releases. (Although they dont have all parts of 2008 supported yet)
Im sure Modelsim wont be too far behind.
Cadence will probably lag, but support will probably come.
02-11-2019 06:59 AM - edited 02-12-2019 08:40 AM
Adding in a vote for essentially any VHDL-2008 support in simulation. Even the most fundamental "quality of life" features aren't implemented for simulation.
Reset_i : in std_logic;
That then gets used in VHDL-2008 style as
if rising_edge(Clk_i) then if Reset_i then
Returns the error in simulation elaboration
ERROR: [XSIM 43-4187] File "<file>.vhd" Line 52 : The "Vhdl 2008 Condition Operator" is not supported yet for simulation.
We had a plan for this project to "keep things simple" and try to use Vivado as a fully integrated design environment, however now we have to choose between the benefits of "new" language fetaures and workflow simplicity. From the years of scattered posts on this matter in the forums, this remains a peristent unsolved problem.
Edit: from the advice of my local FAE, there is limited VHDL-2008 support in the simulator per UG900, Appendix C. However, there are obviously some important exclusions (see my above post) and numeric packages require modifying the library declarations in the source files.