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Visitor herwis
Visitor
18,407 Views
Registered: ‎02-05-2012

Ring Oscillator

Hi,

 

The code below is for a ring oscillator. I am simulating using Xilinx ISE. The simulation stops when I set EN (enable) to one. I don't know what is the probem. I am attaching an image  for more details.

 

`timescale 1 ns / 1 ps
module ring5(EN, clk_s);
input EN;
output clk_s;
wire XLXN_1;
wire XLXN_2;
wire XLXN_3;
wire XLXN_4;
wire XLXN_5;
wire clk_s_DUMMY;
assign clk_s = clk_s_DUMMY;
AND2 XLXI_1 (.I0(EN), .I1(clk_s_DUMMY), .O(XLXN_1));
INV XLXI_2 (.I(XLXN_1), .O(XLXN_2));
INV XLXI_3 (.I(XLXN_2), .O(XLXN_3));
INV XLXI_4 (.I(XLXN_3), .O(XLXN_4));
INV XLXI_5 (.I(XLXN_4), .O(XLXN_5));
INV XLXI_6 (.I(XLXN_5), .O(clk_s_DUMMY));
endmodule

 

xilinx forum.png

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8 Replies
Historian
Historian
18,398 Views
Registered: ‎01-23-2009

Re: Ring Oscillator

Presumably you are doing behavioral simulations - not post place&route simulations.

 

In behavioral simulation, the tool is simulating only the behavior - not timing. In this case, the behavior of an inverter is that the output of the inverter is instantaneously the opposite value of the input. Since this is a ring oscillator, it oscillates with a period of 0ns (an infinite frequency).

 

Verilog (and VHDL as well) are discrete time event driven simulators - it is simulating the advancement of time. In both simulators, time will not advance to the next time "tick" until all events for the current time tick are done. Since your ring is always generating more events as the oscillations of the ring go around and around in 0 time, the time can never advance. Hence time "stops".

 

If you really want to simulate this, you will have to do so using post place&route simulations. In this simulation, the implementation (in LUTs) and the timing of these LUTs are know and will be simulated - hence the oscillations will no longer be in zero time, and time will advance.

 

HOWEVER! Ring oscillators are very bad - particularly bad in FPGAs. There are lots of problems

  1) In mapping these to LUTs, it may well remove everything but a single LUT acting as an inverter - the tool is doing logic optimization and minimization, and will see two inversions as a noop and remove them

  2) The frequency of this ring will be completely dependent on how the design is placed and routed. The frequency you get from this can vary over a huge range from implementation to implementation. You could get an oscillation that is way too fast to do anything with (in the GHz range) or hundreds of time slower - you can't tell, and its very difficult to control.

 

Avrum

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Visitor herwis
Visitor
18,385 Views
Registered: ‎02-05-2012

Re: Ring Oscillator

Hi,

I got the point. But did not know how to do place and rout. I found it in the design panel and did generate it but did not show me the wave form. I am using xilinx ISE 12.1.  would u explain more about how can i use place and rout to show the wave form.

 

Thanks

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Historian
Historian
18,368 Views
Registered: ‎02-25-2008

Re: Ring Oscillator


@herwis wrote:

Hi,

I got the point. But did not know how to do place and rout. I found it in the design panel and did generate it but did not show me the wave form. I am using xilinx ISE 12.1.  would u explain more about how can i use place and rout to show the wave form.

 

Thanks


May I suggest that those who don't understand the most basic of the operation of the tools shouldn't attempt to do something for which an FPGA is uniquely unsuitable.

----------------------------Yes, I do this for a living.
Highlighted
15,906 Views
Registered: ‎11-12-2014

Re: Ring Oscillator

Hai,

                 Try this program...

 

 

module ring5(EN, clk_s,reset);
input EN;
output clk_s;
input reset;
wire XLXN_1;
wire XLXN_2;
wire XLXN_3;
wire XLXN_4;
wire XLXN_5;
wire XLXN_6;
wire clk_s_DUMMY;
assign clk_s = clk_s_DUMMY;
AND2 XLXI_1 (.I0(EN), .I1(clk_s_DUMMY), .O(XLXN_1));
INV XLXI_2 (.I(XLXN_1), .O(XLXN_2));
INV XLXI_3 (.I(XLXN_2), .O(XLXN_3));
INV XLXI_4 (.I(XLXN_3), .O(XLXN_4));
INV XLXI_5 (.I(XLXN_4), .O(XLXN_5));
INV XLXI_6 (.I(XLXN_5), .O(XLXN_6));
or2 XLXI_7 (.I0(XLXN_6), .I1(reset), .O(clk_s_DUMMY));
endmodule

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Xilinx Employee
Xilinx Employee
15,802 Views
Registered: ‎07-21-2014

Re: Ring Oscillator

Hi,

 

Just to add further, you can also use delays in RTL itself (explicitly) so that you can check your behavioral simulation and it will not get stuck when you make EN=1. these delays which you will add in RTL are not synthesizable.

 

thanks,

Shreyas

 

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Teacher muzaffer
Teacher
15,735 Views
Registered: ‎03-31-2012

Re: Ring Oscillator

>> something for which an FPGA is uniquely unsuitable

I beg to disagree. FPGAs are excellent devices for ring oscillators especially in the context of TDC applications to resolve very short periods of time (100s of femtoseconds).
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
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Newbie bairialfie
Newbie
4,243 Views
Registered: ‎12-05-2017

Re: Ring Oscillator

Im facing the same issue as OP. Does anyone can tell me how do i put the time delay for each stage in Verilog or Schematic. Here are my verilog code :

 

module RO5S(EN, RESET, CLK_S, XLXN_1, XLXN_2, XLXN_3, XLXN_4, XLXN_5, XLXN_6);

input EN;
input RESET;
output CLK_S,XLXN_1,XLXN_2,XLXN_3,XLXN_4, XLXN_5,XLXN_6;
wire CLK_S_DUMMY;
wire XLXN_1_DUMMY;
wire XLXN_2_DUMMY;
wire XLXN_3_DUMMY;
wire XLXN_4_DUMMY;
wire XLXN_5_DUMMY;
wire XLXN_6_DUMMY;

assign CLK_S = CLK_S_DUMMY;
assign XLXN_1 = XLXN_1_DUMMY;
assign XLXN_2 = XLXN_2_DUMMY;
assign XLXN_4 = XLXN_4_DUMMY;
assign XLXN_5 = XLXN_5_DUMMY;
assign XLXN_6 = XLXN_6_DUMMY;
assign XLXN_3 = XLXN_3_DUMMY;
INV #5 XLXI_2 (.I(XLXN_1_DUMMY),.O(XLXN_2_DUMMY));
INV #5 XLXI_3 (.I(XLXN_2_DUMMY),.O(XLXN_3_DUMMY));
INV #5 XLXI_4 (.I(XLXN_3_DUMMY),.O(XLXN_4_DUMMY));
INV #5 XLXI_5 (.I(XLXN_4_DUMMY),.O(XLXN_5_DUMMY));
INV #5 XLXI_6 (.I(XLXN_5_DUMMY),.O(XLXN_6_DUMMY));
OR2 XLXI_7 (.I0(RESET),.I1(XLXN_6_DUMMY),.O(CLK_S_DUMMY));
AND2 XLXI_1 (.I0(CLK_S_DUMMY),.I1(EN),.O(XLXN_1_DUMMY));
endmodule

 

I tried putting 5ns (#5) delay for each inverter as you can see in my verilog code and im not sure if i do it correctly. When I try to simulate it on ISIM all i get for each inverter is X (Dont care Value?) value eventho I already set the EN to 1 and RESET 0 on the testbench. 

 

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985 Views
Registered: ‎01-15-2019

Re: Ring Oscillator

The way to solve the unknown state is to use a nand gate for one or all of the inverters and hold one of the gates in reset until the ring reaches a stable state. Then you start up the ring by bringing it out of reset.

 

 

 

 

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