04-08-2021 01:55 AM
You may click the Background button to move the progress bar to the bottom. Check the Tcl console to see at what phase it's running.
04-08-2021 02:23 AM
You can always click cancel to stop the simulation. You could also use a commend like "run 1 ms" to only run for one millisecond of simulation time.
04-08-2021 04:52 AM - edited 04-08-2021 04:56 AM
1st of all you should learn how to post information in a forum. It is difficult for us to extract info from screenshots (that too when pictures are 90 deg rotated) and guess the reasons for failure.
I saw this thread today morning but declined to comment for obvious reasons!
Some examples, but not limited to....
Post RTL code within code-tags </> or as an attached file.
Describe your scenario and problem a bit, be verbose (what do you what to achieve, what you have done up to now, etc).
Post waveform screenshots with proper resolution and orientation.
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem
04-13-2021 08:15 AM
i was trying to test a present cipher code which i had downlaoded from github.
I wanted to run in vivado platform.
i have attatched all the files used for my work.
i have added a testbench verilog file for simulation, but simulation keeps running forever.
can you please suggest me what modifications should i do .