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Registered: ‎10-17-2018

Running simulation without re-compiling Verilog code

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Hello all, I am working on a large project in Vivado. It currently takes about 10 hours to simulate the code I have written. What I am curious about is lowering simulation time. I am only changing the test bench code, and not anything in my design. So I'm wondering if there is a way to run simulation without recompiling my same unchanged code again? Additionally, is there a way to run a simulation longer than 1000nS? Thank you!
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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

Did you enable -incremental option of xvlog&xelab? 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

Did you enable -incremental option of xvlog&xelab? 

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Visitor
Visitor
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Registered: ‎02-22-2018

I cannot see the option -incremental when I do

xvlog -h
xelab -h
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Registered: ‎10-17-2018
Yes, I did.
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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

@freakuency Sorry, the exact option is "--incr".

@jjohnson.wsu This option is supposed to enable incremental analysis/elaboration in simulation. If you didn't delete xsim.dir and still observed re-compilation of unchanged files, please submit a test case.

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Registered: ‎10-17-2018
I was wrong in my approach. I've discovered I had some errors in my testbench and designs that actually caused me to re-approach the problem and solve it. Thank you for responding though!
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