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Registered: ‎03-28-2020

Scrolling text on seven segment display

I was working to scroll the text on the seven segment display and this error popped up, I was following this video from the Lesson 87  https://www.youtube.com/watch?v=V6YUEPRc64M ,I do not know how to fix this error and I guess is something to do with the internal clkdiv.
I send you the file and the screenshots of the errors. 

[DRC INBB-3] Black Box Instances: Cell 'U1' of type 'clkdiv' has undefined contents and is considered a black box.  The contents of this cell must be defined for opt_design to complete successfully.

I am trying to display a message on my Basys 3 Board, and this error keep pooping up. My code is in Vhdl.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Scroll_top is
Port (
btnC: in std_logic;
clk: in std_logic;
seg: out std_logic_vector (6 downto 0);
an: out std_logic_vector (3 downto 0);
dp: out std_logic );
end Scroll_top;
architecture Behavioral of Scroll_top is
component clkdiv is
port (
clk: in std_logic;
clr: in std_logic;
clk190: out std_logic;
clk48: out std_logic
);
end component;
component scroll is
port (
clk: in std_logic;
clr: in std_logic;
x: out std_logic_vector( 15 downto 0)
);
end component;
component x7seg_msg is
port (
x: in std_logic_vector ( 15 downto 0);
clk: in std_logic;
clr: in std_logic;
seg: out std_logic_vector (6 downto 0);
an: out std_logic_vector (3 downto 0);
dp: out std_logic
);
end component;
signal clr: std_logic;
signal clk190: std_logic;
signal clk48: std_logic;
signal x: std_logic_vector (15 downto 0);
begin
clr <= btnC;

U1: clkdiv
port map ( clk => clk,
clr => clr,
clk190 => clk190,
clk48 => clk48
);

U2: scroll
port map ( clk => clk48, clr => clr, x=> x );

U3: x7seg_msg
port map ( x=> x, clk => clk190, clr => clr, seg => seg, an => an, dp => dp);
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Scroll is
Port (clk: in std_logic;
clr: in std_logic;
x: out std_logic_vector(15 downto 0)
);
end Scroll;
architecture Behavioral of Scroll is
signal msg_array : std_logic_vector ( 0 to 63);
constant phone_no: std_logic_vector (63 downto 0) :=x"248D656D1490FFFF";
begin
process(clr,clk)
begin
if clr='1' then
msg_array<= phone_no;
elsif (clk'event and clk ='1') then
msg_array (0 to 59) <= msg_array(4 to 63);
msg_array (60 to 63) <= msg_array(0 to 3);
end if;
end process;
x<= msg_array (0 to 15);

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.all;
entity x7seg_msg is
Port ( x: in std_logic_vector (15 downto 0);
clk: in std_logic;
clr: in std_logic;
seg: out std_logic_vector (6 downto 0);
an: out std_logic_vector (3 downto 0);
dp: out std_logic
);
end x7seg_msg;

architecture Behavioral of x7seg_msg is
signal s: std_logic_vector (1 downto 0);
signal digit: std_logic_vector (3 downto 0);
signal aen: std_logic_vector (3 downto 0);

begin
aen <= "1111";
dp <='1';
--Quad 4 to 1 MUX: mux44
process (s,x)
begin
case s is
when "00" => digit <= x (3 downto 0);
when "01" => digit <= x (7 downto 4);
when "10" => digit <= x (11 downto 8);
when others => digit <= x (15 downto 12);
end case;
end process;
-- 7 decoder
process (digit)
begin
case digit is
when x"0" => seg <= "1000000"; -- "0"
when x"1" => seg <= "1111001"; -- "1"
when x"2" => seg <= "0100100"; -- "2"
when x"3" => seg <= "0110000"; -- "3"
when x"4" => seg <= "0011001"; -- "4"
when x"5" => seg <= "0010010"; -- "5"
when x"6" => seg <= "0000010"; -- "6"
when x"7" => seg <= "1011000"; -- "7"
when x"8" => seg <= "0000000"; -- "8"
when x"9" => seg <= "0010000"; -- "9"
when x"A" => seg <= "0001000"; -- A
when x"b" => seg <= "0000011"; -- b
when x"C" => seg <= "1000110"; -- C
when x"d" => seg <= "1111110"; -- DASH
when x"E" => seg <= "0000110"; -- E
when others => seg <= "1111111"; --blank
end case;
end process;

--Digit select :ancode
process (s,aen)
begin
an <= "1111";
if aen(conv_integer(s)) ='1' then
an(conv_integer(s)) <= '0';
end if ;
end process;
-- 2 bit counter
process (clk, clr)
begin
if clr = '1' then
s <= "00";
elsif clk'event and clk = '1' then
s <= s +1;
end if ;
end process;

 


end Behavioral;

error (1).JPG
error_1.JPG
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Scholar
Scholar
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Registered: ‎08-01-2012

Re: Scrolling text on seven segment display

The error implies you have not added the source code for clkdiv to your project.

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Registered: ‎03-28-2020

Re: Scrolling text on seven segment display

I do not have any idea how to add the source code for clkdiv to the project, do you mean the constraints? I have this on the constrains, I attached the document, could you write the code of the clkdiv or what you mean please

clock.JPG
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Scholar
Scholar
294 Views
Registered: ‎08-01-2012

Re: Scrolling text on seven segment display

clkdiv is simply a component in your code. The compiler cannot find anything that matches the componentin the project. Hence the black box (the compiler doesnt know what it is)

You need to provide the code for it or create an XCI file

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Registered: ‎03-28-2020

Re: Scrolling text on seven segment display

## This file is a general .xdc for the Basys3 rev B board
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
## https://stackoverflow.com/questions/36653359/using-the-clock-on-basys-3

THIS IS WHAT I HAVE FOR THE CONSTRAINTS, how do I create source for that clockdiv???
# Clock signal
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]

# Switches
set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]

# LEDs
set_property PACKAGE_PIN U16 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property PACKAGE_PIN U19 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property PACKAGE_PIN V19 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property PACKAGE_PIN W18 [get_ports {led[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
set_property PACKAGE_PIN U15 [get_ports {led[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
set_property PACKAGE_PIN U14 [get_ports {led[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
set_property PACKAGE_PIN V14 [get_ports {led[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
set_property PACKAGE_PIN V13 [get_ports {led[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
set_property PACKAGE_PIN V3 [get_ports {led[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
set_property PACKAGE_PIN W3 [get_ports {led[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
set_property PACKAGE_PIN U3 [get_ports {led[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
set_property PACKAGE_PIN P3 [get_ports {led[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
set_property PACKAGE_PIN N3 [get_ports {led[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
set_property PACKAGE_PIN P1 [get_ports {led[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
set_property PACKAGE_PIN L1 [get_ports {led[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]


#7 segment display
set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]

set_property PACKAGE_PIN V7 [get_ports dp]
set_property IOSTANDARD LVCMOS33 [get_ports dp]

set_property PACKAGE_PIN U2 [get_ports {an[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
set_property PACKAGE_PIN U4 [get_ports {an[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
set_property PACKAGE_PIN V4 [get_ports {an[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
set_property PACKAGE_PIN W4 [get_ports {an[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]


#Buttons
set_property PACKAGE_PIN U18 [get_ports btnC]
set_property IOSTANDARD LVCMOS33 [get_ports btnC]
set_property PACKAGE_PIN T18 [get_ports btnU]
set_property IOSTANDARD LVCMOS33 [get_ports btnU]
set_property PACKAGE_PIN W19 [get_ports btnL]
set_property IOSTANDARD LVCMOS33 [get_ports btnL]
set_property PACKAGE_PIN T17 [get_ports btnR]
set_property IOSTANDARD LVCMOS33 [get_ports btnR]
set_property PACKAGE_PIN U17 [get_ports btnD]
set_property IOSTANDARD LVCMOS33 [get_ports btnD]


#Pmod Header JA
#Sch name = JA1
set_property PACKAGE_PIN J1 [get_ports {JA[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
#Sch name = JA2
set_property PACKAGE_PIN L2 [get_ports {JA[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
#Sch name = JA3
set_property PACKAGE_PIN J2 [get_ports {JA[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
#Sch name = JA4
set_property PACKAGE_PIN G2 [get_ports {JA[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
#Sch name = JA7
set_property PACKAGE_PIN H1 [get_ports {JA[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
#Sch name = JA8
set_property PACKAGE_PIN K2 [get_ports {JA[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
#Sch name = JA9
set_property PACKAGE_PIN H2 [get_ports {JA[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
#Sch name = JA10
set_property PACKAGE_PIN G3 [get_ports {JA[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]

 

#Pmod Header JB
#Sch name = JB1
set_property PACKAGE_PIN A14 [get_ports {JB[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
#Sch name = JB2
set_property PACKAGE_PIN A16 [get_ports {JB[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
#Sch name = JB3
set_property PACKAGE_PIN B15 [get_ports {JB[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
#Sch name = JB4
set_property PACKAGE_PIN B16 [get_ports {JB[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
#Sch name = JB7
set_property PACKAGE_PIN A15 [get_ports {JB[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
#Sch name = JB8
set_property PACKAGE_PIN A17 [get_ports {JB[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
#Sch name = JB9
set_property PACKAGE_PIN C15 [get_ports {JB[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
#Sch name = JB10
set_property PACKAGE_PIN C16 [get_ports {JB[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]


#Pmod Header JC
#Sch name = JC1
set_property PACKAGE_PIN K17 [get_ports {JC[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
#Sch name = JC2
set_property PACKAGE_PIN M18 [get_ports {JC[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
#Sch name = JC3
set_property PACKAGE_PIN N17 [get_ports {JC[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
#Sch name = JC4
set_property PACKAGE_PIN P18 [get_ports {JC[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
#Sch name = JC7
set_property PACKAGE_PIN L17 [get_ports {JC[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
#Sch name = JC8
set_property PACKAGE_PIN M19 [get_ports {JC[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
#Sch name = JC9
set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
#Sch name = JC10
set_property PACKAGE_PIN R18 [get_ports {JC[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]


#Pmod Header JXADC
#Sch name = XA1_P
set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
#Sch name = XA2_P
set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
#Sch name = XA3_P
set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
#Sch name = XA4_P
set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
#Sch name = XA1_N
set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
#Sch name = XA2_N
set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
#Sch name = XA3_N
set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
#Sch name = XA4_N
set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]

 

#VGA Connector
set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
set_property PACKAGE_PIN P19 [get_ports Hsync]
set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
set_property PACKAGE_PIN R19 [get_ports Vsync]
set_property IOSTANDARD LVCMOS33 [get_ports Vsync]


#USB-RS232 Interface
set_property PACKAGE_PIN B18 [get_ports RsRx]
set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
set_property PACKAGE_PIN A18 [get_ports RsTx]
set_property IOSTANDARD LVCMOS33 [get_ports RsTx]


#USB HID (PS/2)
set_property PACKAGE_PIN C17 [get_ports PS2Clk]
set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
set_property PULLUP true [get_ports PS2Clk]
set_property PACKAGE_PIN B17 [get_ports PS2Data]
set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
set_property PULLUP true [get_ports PS2Data]


#Quad SPI Flash
#Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
#STARTUPE2 primitive.
set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
set_property PACKAGE_PIN K19 [get_ports QspiCSn]
set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]

 

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Scholar
Scholar
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Registered: ‎08-01-2012

Re: Scrolling text on seven segment display

This has nothing to do with constraints. This has to do with source code.

The clkdiv component does something - I assume produces two clocks. I have no idea how it does that without the code.

Where did you get the code from? why cant you get the code for clkdiv?

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Registered: ‎03-28-2020

Re: Scrolling text on seven segment display

I got the code from this video https://www.youtube.com/watch?v=V6YUEPRc64M and I cannot fix the error, I need some help to getting working. 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Scroll_top is
Port (
btnC: in std_logic;
clk: in std_logic;
seg: out std_logic_vector (6 downto 0);
an: out std_logic_vector (3 downto 0);
dp: out std_logic );
end Scroll_top;
architecture Behavioral of Scroll_top is
component clkdiv is
port (
clk: in std_logic;
clr: in std_logic;
clk190: out std_logic;
clk48: out std_logic
);
end component;
component scroll is
port (
clk: in std_logic;
clr: in std_logic;
x: out std_logic_vector( 15 downto 0)
);
end component;
component x7seg_msg is
port (
x: in std_logic_vector ( 15 downto 0);
clk: in std_logic;
clr: in std_logic;
seg: out std_logic_vector (6 downto 0);
an: out std_logic_vector (3 downto 0);
dp: out std_logic
);
end component;
signal clr: std_logic;
signal clk190: std_logic;
signal clk48: std_logic;
signal x: std_logic_vector (15 downto 0);
begin
clr <= btnC;

U1: clkdiv
port map ( clk => clk,
clr => clr,
clk190 => clk190,
clk48 => clk48
);

U2: scroll
port map ( clk => clk48, clr => clr, x=> x );

U3: x7seg_msg
port map ( x=> x, clk => clk190, clr => clr, seg => seg, an => an, dp => dp);
end Behavioral;

 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Scroll is
Port (clk: in std_logic;
clr: in std_logic;
x: out std_logic_vector(15 downto 0)
);
end Scroll;
architecture Behavioral of Scroll is
signal msg_array : std_logic_vector ( 0 to 63);
constant phone_no: std_logic_vector (63 downto 0) :=x"248D656D1490FFFF";
begin
process(clr,clk)
begin
if clr='1' then
msg_array<= phone_no;
elsif (clk'event and clk ='1') then
msg_array (0 to 59) <= msg_array(4 to 63);
msg_array (60 to 63) <= msg_array(0 to 3);
end if;
end process;
x<= msg_array (0 to 15);

end Behavioral;

 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.all;
entity x7seg_msg is
Port ( x: in std_logic_vector (15 downto 0);
clk: in std_logic;
clr: in std_logic;
seg: out std_logic_vector (6 downto 0);
an: out std_logic_vector (3 downto 0);
dp: out std_logic
);
end x7seg_msg;

architecture Behavioral of x7seg_msg is
signal s: std_logic_vector (1 downto 0);
signal digit: std_logic_vector (3 downto 0);
signal aen: std_logic_vector (3 downto 0);

begin
aen <= "1111";
dp <='1';
--Quad 4 to 1 MUX: mux44
process (s,x)
begin
case s is
when "00" => digit <= x (3 downto 0);
when "01" => digit <= x (7 downto 4);
when "10" => digit <= x (11 downto 8);
when others => digit <= x (15 downto 12);
end case;
end process;
-- 7 decoder
process (digit)
begin
case digit is
when x"0" => seg <= "1000000"; -- "0"
when x"1" => seg <= "1111001"; -- "1"
when x"2" => seg <= "0100100"; -- "2"
when x"3" => seg <= "0110000"; -- "3"
when x"4" => seg <= "0011001"; -- "4"
when x"5" => seg <= "0010010"; -- "5"
when x"6" => seg <= "0000010"; -- "6"
when x"7" => seg <= "1011000"; -- "7"
when x"8" => seg <= "0000000"; -- "8"
when x"9" => seg <= "0010000"; -- "9"
when x"A" => seg <= "0001000"; -- A
when x"b" => seg <= "0000011"; -- b
when x"C" => seg <= "1000110"; -- C
when x"d" => seg <= "1111110"; -- DASH
when x"E" => seg <= "0000110"; -- E
when others => seg <= "1111111"; --blank
end case;
end process;

--Digit select :ancode
process (s,aen)
begin
an <= "1111";
if aen(conv_integer(s)) ='1' then
an(conv_integer(s)) <= '0';
end if ;
end process;
-- 2 bit counter
process (clk, clr)
begin
if clr = '1' then
s <= "00";
elsif clk'event and clk = '1' then
s <= s +1;
end if ;
end process;

 


end Behavioral;

This tutorial on Scrolling the 7-segment Display accompanies the book Digital Design Using Digilent FPGA Boards - VHDL / Active-HDL Edition which contains ov...
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Scholar
Scholar
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Registered: ‎08-01-2012

Re: Scrolling text on seven segment display

Im not really sure what you're asking for now. The problem is you're missing some source code. You'll either need to find it somewhere or write it yourself.

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