I have multiple VHDL files in my Vivado 2019.1 project. I intend to run a behavioral simulation on a specific file of the project but the simulator always picks up a default file.
Can anyone help with this?
Just found the solution, Hope this helps every beginner encountering the issue.
To simulate a desired file in the working project. Go to: Simulation Sources --> sim_1 --> *Select File*
Then right-click and select "Set as Top".
Then run the behavioral simulation. It'll run your desired file.