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Adventurer
Adventurer
8,606 Views
Registered: ‎10-01-2014

Setting up clock wizard doubt

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Hi guys,

 

I have one doubt in using the clock wizard in the IP intregrator design. My FPGA, VC707 provides differential clock signals individually, however the clock wizard requires a single clock label for its differential input. After checking the master file of the FPGA I notice that this signal is not provided.

 

Please see the picture:

 

capture1.PNG

 

Can anyone tell me how can I fix this problem?

 

Please see attached the .xdc file for my FPGA.

 

Many thanks,

 

Rodolfo

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Teacher
Teacher
16,649 Views
Registered: ‎03-31-2012

Re: Setting up clock wizard doubt

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That is mostly correct. You have to change the IOSTANDARD lines to sys_diff_clock_clk_p/n too.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Voyager
Voyager
8,596 Views
Registered: ‎04-21-2014

Re: Setting up clock wizard doubt

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That is an interface not a signal.  Did you try connection automation?  

 

If not, take a look at your top level wrapper and you should see an _p and an _n version of the ports. 

 

Assign the _p to the pad based on your XDC/UCF/schematic.

 

If you did use connection automation (I haven't used the VC709 in awhile), it should automatically get connected to the correct pads assuming you selected the correct board level interface when prompted.  You can verify this by opening your synthesized design and seeing where the pins were assigned.

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
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Adventurer
Adventurer
8,569 Views
Registered: ‎10-01-2014

Re: Setting up clock wizard doubt

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Hi morgan,

 

Many thanks for your reply.  I understood waht you mean, but can you just confirm this is the right procedure:

 

1) I did use the connection automation to get the respective labels, as you can see:

 

capture1.PNG

2) Then I create the HDL wrapper of the design, wich assigned the clock as:

 

Capture2.PNG

 

3) I edit the master file of the FPGA and placed the labels sys_diff_clock_clk_n and sys_diff_clock_clk_p in the right pins:

 

Capture2.PNG

 

 

Is this the right procedure?

 

Many thanks,

 

Rodolfo

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Teacher
Teacher
16,650 Views
Registered: ‎03-31-2012

Re: Setting up clock wizard doubt

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That is mostly correct. You have to change the IOSTANDARD lines to sys_diff_clock_clk_p/n too.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post

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Adventurer
Adventurer
8,551 Views
Registered: ‎10-01-2014

Re: Setting up clock wizard doubt

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Many thanks, now I get it!
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