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Newbie hertok
Registered: ‎01-08-2010

Signals to port out assignment does not work on Isim

Hi everyone,


I am quite new to Xilinx ISE and ISim. I hope this is the right place to post this. 


I am using ISE WebPack. 


I have a project to implement pipelined MIPS design. I have written all necessary VHDL codes and tried to run a simulation on ISim. I selected Spartan3 as target hardware. 


I will only post the first part of the whole code since that is the starting point of the problem. 


library IEEE;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity InstructionFetch is
    Port ( PC : in  STD_LOGIC_VECTOR (7 downto 0);  -- program counter
           InstructionCode : out  STD_LOGIC_VECTOR (31 downto 0); -- instruction being fetched
           PCNext : out  STD_LOGIC_VECTOR (7 downto 0); -- program counter for the next cycle
              clk : in STD_LOGIC); -- the clock signal
end InstructionFetch;

architecture Behavioral of InstructionFetch is
    --signal PC : std_logic_vector(7 downto 0);
   signal PCtemp : std_logic_vector(7 downto 0);
   signal PCaddtemp : std_logic_vector(7 downto 0);
    signal Instruction :  std_logic_vector(31 downto 0);
-- Insert SPIM Machine Language Test Program Here
          constant mem0 : std_logic_vector(31 downto 0) := (
--          Field   | op | rs | rt | rd ?addr/immed|
                (B"00000010010110010000110000001000")); -- addi $s2,$s2,3
                constant mem1 : std_logic_vector(31 downto 0) := (
                (B"00000010001100010010100000001000")); -- addi $s1,$s1,5
          constant mem2 : std_logic_vector(31 downto 0) := (
                (B"10101110011100100000000000110000")); -- sw $s2, 48($s3)
          constant mem3 : std_logic_vector(31 downto 0) := (
                (B"10001110010101000000000000000000")); -- lw $s4,0($s2)
    -- Increment PC by 4
    PCtemp <= PC;
    -- Load the next program counter
    loadpc : process is
    wait until (clk'EVENT) and (clk = '1');
    -- if the first instruction is being fetched use PC = 00000000 otherwise use next pc
        if PCtemp = "00000000" then
            PCaddtemp <= PCtemp;
            PCaddtemp <= PCtemp + 4;
        end if;
        case PCtemp(4 downto 2) is
            when "000" => Instruction <= mem0;
            when "001" => Instruction <= mem1;
            when "010" => Instruction <= mem2;
            when "011" => Instruction <= mem3;
            when others => Instruction <= mem0;
        end case;   
    end process loadpc;
    PCNext <= PCtemp;
    InstructionCode <= Instruction;
end Behavioral;

This code has no syntax error. I also created testbench file and other necessary files.


When i run the simulation, I can see that the signals declared in this code change during execution. But the simulation never assigns the values of PCtemp and instruction to the written output ports above. ISim window shows UUUUU... as the value for output ports.


Could you please tell me why this is happening? and show me how to fix it?


Thanks a lot... 

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2 Replies
Registered: ‎09-15-2008

Re: Signals to port out assignment does not work on Isim


you assign PC to (PCtemp <= PC;) and then PCtemp to PCNext (PCNext <= PCtemp;).

You increment PCaddtemp adding 4 to PCtemp but you never use it. Maybe there's some confusion about PCtemp and PCaddtemp in your coding...

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Newbie hertok
Registered: ‎01-08-2010

Re: Signals to port out assignment does not work on Isim



Thanks for the reply.


I dont think it has anything to do with PCaddtemp. 

The main problem is whatever I do, I cant assign  values to the output ports. I even assigned binary values to PCNext and InstructionCode but they still have values UUUUUU... on the ISim. Thus, I cant transfer data from this module to the next one.



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