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Observer
Observer
8,974 Views
Registered: ‎02-20-2014

Sim problems with FIFO_DUALCLOCK_MACRO

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Hi,

 

I'm trying to compile my design using the FIFO_DUALCLOCK_MACROs, but I get an error message reporting some issue with the Macro itself. Does anyone know how to get around this?

 

ERROR: [VRFC 10-704] formal rdcount has no actual or default value [/proj/buildscratch/builds/2014.2/continuous/20140611

121610/data/vhdl/src/unimacro/FIFO_DUALCLOCK_MACRO.vhd:53]

 

ERROR: [VRFC 10-704] formal wrcount has no actual or default value [/proj/buildscratch/builds/2014.2/continuous/20140611

121610/data/vhdl/src/unimacro/FIFO_DUALCLOCK_MACRO.vhd:55]

 

ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit analogfrontendtb in library work failed.

 

ERROR: [Runs 36-25] xelab application returned error(s). Please see 'd:/Projects/GuardRec/xDC/FPGA/sim/prj/xdc_audio_afe

_sim/xdc_audio_afe_sim.sim/sim_1/behav/xelab.log' file for more details.

 

ERROR: [Common 17-69] Command failed: Failed to compile the design!

 

Another question about the instance: I'm using a zynq-7010 device, but in the source it does not say anything about zynq-support, only "7series"....does it not support Zynq?

 

br,

cja

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Xilinx Employee
Xilinx Employee
15,418 Views
Registered: ‎09-20-2012

Re: Sim problems with FIFO_DUALCLOCK_MACRO

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Hi,

 

signal tmp1: std_logic_vector(9 downto 0);
signal tmp2 : std_logic_vector(9 downto 0);

 

Declare two dummy signals and connect them to RDCOUNT and WRCOUNT ports of the macro respectively.

 

RDCOUNT => open errors out but RDCOUNT=> tmp1(9 downto 0) does not. 


Single bit output ports can be left unconnected (OPEN) but vector ports do need a width specified even if unused.

 

Hope this helps.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
8,969 Views
Registered: ‎09-20-2012

Re: Sim problems with FIFO_DUALCLOCK_MACRO

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Hi,

 

If it supports 7 series it supports Zynq too.

 

Can you show us the instantiation of macro in your design?

 

Can you make sure that you are following the instantiation template provided at page-61 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug953-vivado-7series-libraries.pdf

 

Thanks,

Deepika.

 

 

Thanks,
Deepika.
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Observer
Observer
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Registered: ‎02-20-2014

Re: Sim problems with FIFO_DUALCLOCK_MACRO

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Here is my instance:

 

u1_ch1 : entity unimacro.FIFO_DUALCLOCK_MACRO

    generic map (

      DEVICE                  => "7SERIES",  -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES"

      ALMOST_FULL_OFFSET      => X"0100",    -- Sets almost full threshold

      ALMOST_EMPTY_OFFSET     => X"0100",    -- Sets the almost empty threshold

      DATA_WIDTH              => 36,  -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")

      FIFO_SIZE               => "36Kb",     -- Target BRAM, "18Kb" or "36Kb"

      FIRST_WORD_FALL_THROUGH => false)  -- Sets the FIFO FWFT to TRUE or FALSE

    port map (

      ALMOSTEMPTY => open,

      ALMOSTFULL  => fifoAlmostFull(1),

      DO          => dataFromFifoCh1,

      EMPTY       => open,

      FULL        => open,

      RDCOUNT     => open,  --RDCOUNT,  -- Output read count, width determined by FIFO depth

      RDERR       => open,

      WRCOUNT     => open,  --WRCOUNT,  -- Output write count, width determined by FIFO depth

      WRERR       => open,

      DI          => dataToFifoCh1,

      RDCLK       => clk,

      RDEN        => fifoReadEnable(1),

      RST         => reset,

      WRCLK       => sclk,

      WREN        => fifoWriteEnable(1));

 

I copied the instance from UG953...

 

-cja

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Xilinx Employee
Xilinx Employee
15,419 Views
Registered: ‎09-20-2012

Re: Sim problems with FIFO_DUALCLOCK_MACRO

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Hi,

 

signal tmp1: std_logic_vector(9 downto 0);
signal tmp2 : std_logic_vector(9 downto 0);

 

Declare two dummy signals and connect them to RDCOUNT and WRCOUNT ports of the macro respectively.

 

RDCOUNT => open errors out but RDCOUNT=> tmp1(9 downto 0) does not. 


Single bit output ports can be left unconnected (OPEN) but vector ports do need a width specified even if unused.

 

Hope this helps.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

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Observer
Observer
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Registered: ‎02-20-2014

Re: Sim problems with FIFO_DUALCLOCK_MACRO

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OK, this works. But, I am not sure I like this. To create unnecessary dummy signals only creates unwanted "mess" in my code....

 

-cja

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