06-05-2018 05:47 AM
I'm having some trouble writing and reading data to the RAM model (emuating OCM) and the sparse memory model (emuating DDR) via the AXI HP ports in a simulation.
I've tried attaching a DMA, a DataMover and an AXI traffic generator to a AXI HP port on Zynq via an AXI SmartConnect and simulating some traffic between the Zynq and the PL but to no avail (AXI read transactions time out even though the memory is preloaded with random data and AXI write transactions return with BRESP = 0 but when I try to backdoor read the data back I get x).
Are there any example projects that can be simulated where AXI transactions on AXI HP or ACP ports are working?
06-05-2018 01:17 PM
06-05-2018 01:50 PM