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Observer
Observer
1,348 Views
Registered: ‎12-14-2013

Simulating DMA access via AXI HP ports with Zynq VIP

Hi!

I'm having some trouble writing and reading data to the RAM model (emuating OCM) and the sparse memory model (emuating DDR) via the AXI HP ports in a simulation.

I've tried attaching a DMA, a DataMover and an AXI traffic generator to a AXI HP port on Zynq via an AXI SmartConnect and simulating some traffic between the Zynq and the PL but to no avail (AXI read transactions time out even though the memory is preloaded with random data and AXI write transactions return with BRESP = 0 but when I try to backdoor read the data back I get x).

Are there any example projects that can be simulated where AXI transactions on AXI HP or ACP ports are working?

Thanks,
Z

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Observer
Observer
1,295 Views
Registered: ‎12-14-2013

Re: Simulating DMA access via AXI HP ports with Zynq VIP

I've failed to mention that I'm using Vivado 2018.1 simulator on Win 10.

I've also attached my project if anyone wants to take a look.

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Observer
Observer
1,285 Views
Registered: ‎12-14-2013

Re: Simulating DMA access via AXI HP ports with Zynq VIP

Digging further I can see that there's another thread regarding this issue:

Zynq 7000 Verification IP S_AXI_ACP doesn't-assert RVALID

 

Are there any updates or workarounds?

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