05-26-2015 01:40 AM
Hi,
I am using Vivado 2014.2 (Win7, 64bit) and try to simulate the axi_quad_spi ip with ModelSim (10.3b). However, I encounter the following error after launching the simulation:
# vsim -do "do {***/sim_1/behav/top_tb.do}"
...
# Loading axi_quad_spi_v3_2.qspi_core_interface(imp)
# Loading axi_quad_spi_v3_2.reset_sync_module(imp)
# Loading axi_quad_spi_v3_2.cross_clk_sync_fifo_1(imp)
# ** Error: (vsim-13) Recompile proc_common_v4_0.async_fifo_fg(implementation) because fifo_generator_v12_0.fifo_generator_v12_0 has changed.
#
# Load interrupted
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ***\sim_1\behav\top_tb.do PAUSED at line 252
Simulation libraries have been compiled via following tcl command: compile_simlib -family virtex7 -language all -library all -simulator modelsim
It seems to me that ip axi_quad_spi (v3.2) uses some legacy fifo versions which are not compiled into the simulation libraries for modelsim.
Can anybody direct me to solve the problem?
Thanks, Jan
05-26-2015 01:48 AM - edited 05-26-2015 01:54 AM
Hii @jhk,
Check the following AR:
http://www.xilinx.com/support/answers/60193.html
--Syed
--------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
--------------------------------------------------
05-26-2015 01:48 AM - edited 05-26-2015 01:54 AM
Hii @jhk,
Check the following AR:
http://www.xilinx.com/support/answers/60193.html
--Syed
--------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
--------------------------------------------------
05-26-2015 02:16 AM
Many thanks @syedz!
set_param ips.useProjectLanguageSubcoreFileDiscovery true
as denoted in AR #60193, was the solution.
Jan