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Visitor mkabra
Visitor
8,795 Views
Registered: ‎10-21-2009

Simulating PCIe block in ISIM. HDLCompiler error 1044.

Hi,

 

I'm working PCIe end block plus IP Core that is generated with coregen. I followed the steps listed here http://forums.xilinx.com/xlnx/board/crawl_message?board.id=PCIe&message.id=1088 by  hakanaydin

 

The core and the files are generated properly. But when I try to simulate the design, I get the error 

 ERROR:HDLCompiler:1044 - "Unknown" Line 0: /data/Xilinx/11.1/ISE/verilog/hdp/lin64/xip/gt11_ver/@g@t11_@s@w@i@f@t.sdb was created using an incompatible version_number, backward compatibility is not supported yet
ERROR:HDLCompiler:559 - "/build/xfndry10/L.57/rtf/verilog/src/unisims/GT11.v" Line 2436: Could not find module/primitive <GT11_SWIFT>.

 

I'm using ISIM to simulate the design on 64 bit linux. The PCIe end block plus version is 1.11 and I'm using ISE 11.1. I can attach the details of the simulation run if required.

 

Can anyone tell me whats the problem?

mayank

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13 Replies
Xilinx Employee
Xilinx Employee
8,770 Views
Registered: ‎08-15-2007

Re: Simulating PCIe block in ISIM. HDLCompiler error 1044.

This is a known issue with the ISE Simulator 11.3 tool.  A patch is available via Xilinx Answer 33727.  This answer record should be made available within 24 hrs from this edit.

 

 
Message Edited by edv on 10-29-2009 03:43 PM
Eddie
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Observer manu
Observer
8,733 Views
Registered: ‎11-21-2007

Re: Simulating PCIe block in ISIM. HDLCompiler error 1044.

Hello,

 

I seem to have a similar issue .

 

I am on Windows XP, I use ISE 11.3 and I have imported one by one the files generated for the PCIe example design v1_12 by Core Generator.

I had to add

`include "use_newinterrupt.v"

 

in a few files and to add to the search order path

 

X:/Firmware/FPGA/src/PCIe/PB_PCIe/OneLane/Virtex5/src/ips/GTPs/pcie_v1_12/ipcore_dir/single_core/simulation

X:/Firmware/FPGA/src/PCIe/PB_PCIe/OneLane/Virtex5/src/ips/GTPs/pcie_v1_12/ipcore_dir/single_core/source

 

so that the design files can be found and that all the design files compile fine.

But now I am really stuck with the following 2 errors:

 

 

ERROR:HDLCompiler:559 - "N:/L.57/rtf/verilog/src/unisims/PCIE_2_0.v" Line 2957: Could not find module/primitive <B_PCIE_2_0>.
ERROR:HDLCompiler:559 - "N:/L.57/rtf/verilog/src/unisims/GTXE1.v" Line 2500: Could not find module/primitive <B_GTXE1>.

 

 

...which bring me here!

 

I have looked onto the answer records and found nothing concerning this problem.

Looking at the PCIE_2_0.v file in $XILINX\verilog\src\unisims, the revision history mentions this file is for Xilinx version 10.1.

Could this be the problem.

Nevertheless I did install the ISE11.3 service pack.

 

So can you let me know if I am facing the same problem as mentioned in the post and if so when are we getting the patch?

Otherwise, any clue on what I did wrong ?

thanks for your help,

Regards,

Manu

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Observer manu
Observer
8,730 Views
Registered: ‎11-21-2007

Re: Simulating PCIe block in ISIM. HDLCompiler error 1044.

Hi,

 

I just found an answer record, but it is specific to 64 bit Windows install apparently and I am on 32bits.

(http://www.xilinx.com/support/answers/33551.htm)

ISE Simulator (ISim) - Simulator:778 - Static elaboration of top level Verilog design unit(s) in library work failed

 

Is this at all releavant?

Thanks,

Regards,

Manu

 

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Visitor mkabra
Visitor
8,728 Views
Registered: ‎10-21-2009

Re: Simulating PCIe block in ISIM. HDLCompiler error 1044.

I don't the think the answer record you mention is relevant to the problem.

 

mayank

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Observer manu
Observer
8,724 Views
Registered: ‎11-21-2007

Re: Simulating PCIe block in ISIM. HDLCompiler error 1044.

Hi,

Thank you for your reply.

I actually went ahead and applied the patch, but no difference.(then i have rolled back to my 11.3 for Windows 32bits now)

I was reading my posts again and I have maybe not been very clear.

So, I am trying to simulate with ISIM in Project Navigator the default PCIe core example that Coregen generates (VHDL top level).

It was actually far from easy to make the ISE project compile correctly all the .vhd or .v files...as I am a vhdl guy, but the good point is that I get to know a bit more about verilog...

But i was not anticipating problems with Xilinx own simulator, as it looks like the Xilinx developers managed to simulate the design correctly with other simulators.

Actually it's a bit weird that they don't use their own tool...

But, well, I hope we can help soon.

Regards,

Manu

 

 

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Visitor mkabra
Visitor
8,722 Views
Registered: ‎10-21-2009

Re: Simulating PCIe block in ISIM. HDLCompiler error 1044.

Yeah, the coregen has lots of issue. In particular, PCIE endpoint block plus v 1.12 is buggy. It wouldn't even generate the .ngc file with 1.12 . So I decided to use 1.11 and it works.

 

I think the problem with ISIM is that it isn't properly integrated yet with ISE. Earlier all simulations were supposed to be done using external simulators. But they decided to integrate the simulator within ISE which is good news, but either they haven't integrated or verified it properly. But atleast they know that this is an issue and are working on it.

 

mayank

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Observer manu
Observer
8,705 Views
Registered: ‎11-21-2007

Re: Simulating PCIe block in ISIM. HDLCompiler error 1044.

Hi,

 

I have also reversed to ISE11.2 to use PCIe Endpoint block plus v1.11 under ISIM.

All simulates now.

I don't know if you are aware but there is a patch for some source files released for  PCIe Endpoint block plus v1.12 but that can/should be applied to v1.11 as they correct some bugs.

just in case, here ais the list of know issues:

http://www.xilinx.com/support/answers/32741.htm

 

The zip containing the workaround is here:
ftp://ftp.xilinx.com/pub/applications/pci/ar33278_bp_v1_12_files.zip

 

Regards,

Manu

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Xilinx Employee
Xilinx Employee
8,668 Views
Registered: ‎08-15-2007

Re: Simulating PCIe block in ISIM. HDLCompiler error 1044.

Please refer to my earlier thread.  A new Xilinx Answer has been published documenting the issue and solution.  The 11.3 patch will resolve the HDLCompiler:1044 and HDLCompiler:559 associated with the GT11 libraries. 

 

http://www.xilinx.com/support/answers/33727.htm (should be made available within 24 hrs)


Please contact Xilinx Technical Support via a WebCase if you require further assistance with this issue.

 

 

Eddie
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Visitor mkabra
Visitor
8,656 Views
Registered: ‎10-21-2009

Re: Simulating PCIe block in ISIM. HDLCompiler error 1044.

Thanks Eddie! I'll check it out.
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Observer manu
Observer
4,460 Views
Registered: ‎11-21-2007

Re: Simulating PCIe block in ISIM. HDLCompiler error 1044.

Hi Guys,

 

Just so you know, I applied the patch and it didn't solve the simulation errors I mentioned earlier on.

And you Mayank?

Thanks,

Manu

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Visitor mkabra
Visitor
4,454 Views
Registered: ‎10-21-2009

Re: Simulating PCIe block in ISIM. HDLCompiler error 1044.

I haven't checked it out yet. I'll post a reply when I try it out.

 

mayank

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Xilinx Employee
Xilinx Employee
4,451 Views
Registered: ‎08-15-2007

Re: Simulating PCIe block in ISIM. HDLCompiler error 1044.

Manu,

 

Can you follow-up with Xilinx Technical Support via a WebCase to learn whether the patch is not covering your issue?  When doing so, please refer to this forum thread in the case notes so the Applications Engineer is aware of the topic.

 

Please also send me a PM (Private message) with the case number so I can chime in if needed.

 

Thanks.

 

Eddie
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Observer manu
Observer
4,435 Views
Registered: ‎11-21-2007

Re: Simulating PCIe block in ISIM. HDLCompiler error 1044.

Hello Eddie,

 

That's done.

I'll send you the webcase in a PM.

Thanks,

Manu

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