10-21-2009 02:42 PM
I'm working PCIe end block plus IP Core that is generated with coregen. I followed the steps listed here http://forums.xilinx.com/xlnx/board/crawl_message?board.id=PCIe&message.id=1088 by hakanaydin
The core and the files are generated properly. But when I try to simulate the design, I get the error
ERROR:HDLCompiler:1044 - "Unknown" Line 0: /data/Xilinx/11.1/ISE/verilog/hdp/lin64/xip/gt11_ver/@g@t11_@s@w@i@email@example.com was created using an incompatible version_number, backward compatibility is not supported yet
ERROR:HDLCompiler:559 - "/build/xfndry10/L.57/rtf/verilog/src/unisims/GT11.v" Line 2436: Could not find module/primitive <GT11_SWIFT>.
I'm using ISIM to simulate the design on 64 bit linux. The PCIe end block plus version is 1.11 and I'm using ISE 11.1. I can attach the details of the simulation run if required.
Can anyone tell me whats the problem?
10-23-2009 02:43 PM - edited 10-29-2009 03:43 PM
This is a known issue with the ISE Simulator 11.3 tool. A patch is available via Xilinx Answer 33727. This answer record should be made available within 24 hrs from this edit.
10-27-2009 09:51 AM
I seem to have a similar issue .
I am on Windows XP, I use ISE 11.3 and I have imported one by one the files generated for the PCIe example design v1_12 by Core Generator.
I had to add
in a few files and to add to the search order path
so that the design files can be found and that all the design files compile fine.
But now I am really stuck with the following 2 errors:
ERROR:HDLCompiler:559 - "N:/L.57/rtf/verilog/src/unisims/PCIE_2_0.v" Line 2957: Could not find module/primitive <B_PCIE_2_0>.
ERROR:HDLCompiler:559 - "N:/L.57/rtf/verilog/src/unisims/GTXE1.v" Line 2500: Could not find module/primitive <B_GTXE1>.
...which bring me here!
I have looked onto the answer records and found nothing concerning this problem.
Looking at the PCIE_2_0.v file in $XILINX\verilog\src\unisims, the revision history mentions this file is for Xilinx version 10.1.
Could this be the problem.
Nevertheless I did install the ISE11.3 service pack.
So can you let me know if I am facing the same problem as mentioned in the post and if so when are we getting the patch?
Otherwise, any clue on what I did wrong ?
thanks for your help,
10-27-2009 10:23 AM
I just found an answer record, but it is specific to 64 bit Windows install apparently and I am on 32bits.
ISE Simulator (ISim) - Simulator:778 - Static elaboration of top level Verilog design unit(s) in library work failed
Is this at all releavant?
10-27-2009 01:53 PM
Thank you for your reply.
I actually went ahead and applied the patch, but no difference.(then i have rolled back to my 11.3 for Windows 32bits now)
I was reading my posts again and I have maybe not been very clear.
So, I am trying to simulate with ISIM in Project Navigator the default PCIe core example that Coregen generates (VHDL top level).
It was actually far from easy to make the ISE project compile correctly all the .vhd or .v files...as I am a vhdl guy, but the good point is that I get to know a bit more about verilog...
But i was not anticipating problems with Xilinx own simulator, as it looks like the Xilinx developers managed to simulate the design correctly with other simulators.
Actually it's a bit weird that they don't use their own tool...
But, well, I hope we can help soon.
10-27-2009 01:59 PM
Yeah, the coregen has lots of issue. In particular, PCIE endpoint block plus v 1.12 is buggy. It wouldn't even generate the .ngc file with 1.12 . So I decided to use 1.11 and it works.
I think the problem with ISIM is that it isn't properly integrated yet with ISE. Earlier all simulations were supposed to be done using external simulators. But they decided to integrate the simulator within ISE which is good news, but either they haven't integrated or verified it properly. But atleast they know that this is an issue and are working on it.
10-28-2009 06:58 AM
I have also reversed to ISE11.2 to use PCIe Endpoint block plus v1.11 under ISIM.
All simulates now.
I don't know if you are aware but there is a patch for some source files released for PCIe Endpoint block plus v1.12 but that can/should be applied to v1.11 as they correct some bugs.
just in case, here ais the list of know issues:
The zip containing the workaround is here:
10-29-2009 03:46 PM
Please refer to my earlier thread. A new Xilinx Answer has been published documenting the issue and solution. The 11.3 patch will resolve the HDLCompiler:1044 and HDLCompiler:559 associated with the GT11 libraries.
http://www.xilinx.com/support/answers/33727.htm (should be made available within 24 hrs)
Please contact Xilinx Technical Support via a WebCase if you require further assistance with this issue.
11-03-2009 06:10 AM
Just so you know, I applied the patch and it didn't solve the simulation errors I mentioned earlier on.
And you Mayank?
11-03-2009 12:27 PM
Can you follow-up with Xilinx Technical Support via a WebCase to learn whether the patch is not covering your issue? When doing so, please refer to this forum thread in the case notes so the Applications Engineer is aware of the topic.
Please also send me a PM (Private message) with the case number so I can chime in if needed.