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checkandmate
Visitor
Visitor
3,312 Views
Registered: ‎05-02-2017

Simulating Vivado Encrypted Fles in Modelsim

Hi,

 

I have an interpolator that now consists of numerous Adder/Subtractor v12.0 IP blocks. I now want to include it into my Modelsim PE 10.6 simulation. This is the structure in the hierarchy of my project in Vivado 2015.4:

interpolation_hierarchy.PNG

 

The issue is that c_addsub_v12_0_8 is encrypted as shown above. I get the following errors:

# ** Error: ../../../../../rtl/ntc_16tap_interpolator_wrapper_v1_0/hdl/ntc_16tap_interpolator_c_addsub_0_0/sim/ntc_16tap_interpolator_c_addsub_0_0.vhd(56): (vcom-1598) Library "c_addsub_v12_0_8" not found.
# ** Error: ../../../../../rtl/ntc_16tap_interpolator_wrapper_v1_0/hdl/ntc_16tap_interpolator_c_addsub_0_0/sim/ntc_16tap_interpolator_c_addsub_0_0.vhd(57): (vcom-1136) Unknown identifier "c_addsub_v12_0_8".
# ** Error: ../../../../../rtl/ntc_16tap_interpolator_wrapper_v1_0/hdl/ntc_16tap_interpolator_c_addsub_0_0/sim/ntc_16tap_interpolator_c_addsub_0_0.vhd(59): VHDL Compiler exiting
# End time: 14:49:46 on Jul 28,2017, Elapsed time: 0:00:00
# Errors: 3, Warnings: 1
# ** Error: C:/modeltech_pe_10.6/win32pe/vcom failed.

The errors I get are exactly as shown in this link. However, implementing the recommended solution changes nothing in my simulation.

 

I have also tried using the compile_simlib command (AR# 64083) and copying the new modelsim.ini file into my simulation directory to no avail. All other posts on the forum that I have seen talk about protected files which is not my case.

 

Thank you!

Mate

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graces
Moderator
Moderator
3,246 Views
Registered: ‎07-16-2008

A few things to check.

1. Did you complete compile_simlib successfully? Review compile_simlib.log and see if there're errors.

2. It looks you're using 32-bit Modelsim PE. Note by default compile_simlib is run in 64-bit mode. Add -32bit switch to perform the compilation in 32-bit mode.

3. Did you launch Modelsim stand-alone or from within Vivado GUI? If you create your custom simulation script, make sure you compile all necessary sim files to the correct library. It's recommended that you run export_simulation (File > Export > Export Simulation) and take the generated compile/elaborate/simulate.do as reference.

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checkandmate
Visitor
Visitor
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Registered: ‎05-02-2017

Hi graces,

 

1. No errors in compile_simlib.log.

2. The -32bit switch when running compile_simlib was included.

3. I am launching Modelsim from a script (outline of script below). I ran export_simulation but there was only a run.do file which looked like the compile.do file, although it's missing the ntc_16tap_interpolator.v file.

 

The error occurs within compile.do. This is how my sim script was setup:

# Auto generated by Vivado for 'behavioral' simulation
vlib work
vlib msim

vlib msim/xil_defaultlib

vmap xil_defaultlib msim/xil_defaultlib

# System verilog modules compilation vlog -incr -sv -work xil_defaultlib "+incdir+../../../../../rtl/verilog" "+incdir+../../../../../sim/testcases" \ # list of .sv modules, not relevant
# Verilog modules compilation vlog -incr -work xil_defaultlib "+incdir+../../../../../rtl/verilog" "+incdir+../../../../../sim/testcases" \ "../../../../../rtl/ntc_16tap_interpolator_wrapper_v1_0/hdl/ntc_16tap_interpolator_wrapper.v" \
"../../../../../rtl/ntc_16tap_interpolator_wrapper_v1_0/hdl/ntc_16tap_interpolator.v" \ # ...other modules
# WHERE ERROR OCCURS vcom -work xil_defaultlib \ "../../../../../rtl/ntc_16tap_interpolator_wrapper_v1_0/hdl/ntc_16tap_interpolator_c_addsub_0_0/sim/ntc_16tap_interpolator_c_addsub_0_0.vhd" \
# ...other addsub modules which are vhd files that call the encrypted files

I'm trying to figure out how to "add" the pre-compiled files before I reach the vcom command.

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graces
Moderator
Moderator
3,178 Views
Registered: ‎07-16-2008

Well, I'd suggest that you compare the custom script with the compile.do generated by Vivado. 

Most likely you didn't compile the IP sim files to the correct library. Instead, you compiled all sources to the default library.

-----------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
-----------------------------------------------------------------------------------------------------------------------
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