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Contributor
Contributor
659 Views
Registered: ‎03-29-2016

Simulating Xilinx Viterbi TestBench

Hey,

I am attempting to use the Xilinx Viterbi Core provided Testbench (v9.1.5) and receiving the following error (Vivado 2015.4):

 

ERROR: [VRFC 10-149] 'viterbi_v9_1_5' is not compiled in library viterbi_v9_1_5 [/home/usr/vivado_projects/csp/csp.ip_user_files/bd/convenc_test/ip/convenc_test_viterbi_0_0/synth/convenc_test_viterbi_0_0.vhd:57]

 

Line 56, 56:

LIBRARY viterbi_v9_1_5;
USE viterbi_v9_1_5.viterbi_v9_1_5;

 

 

In the attached image you can see the unit appearing in the design sources but not in the simulation sources. Both of the files are set to library work. Although the same error occurs when I move them both to xildefault_lib.

 

Any idea how to make this work? Thanks.

vit_sim_error.png
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1 Reply
Xilinx Employee
Xilinx Employee
613 Views
Registered: ‎02-06-2013

Re: Simulating Xilinx Viterbi TestBench

Hi

 

viterbi_v9_1_vh_rfs.vhd file should be compiled to its associated library(viterbi_v9_1_7) as mentioned in the error message.

 

report_compile_order command at the tcl console will give you the files and their associated libraries which you need to compile the files

 

Vivado also generate the simulation scripts with correct order and file mapping with export_simulation command which you can use

 

Refer UG900 for more details.

Regards,

Satish

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