03-18-2015 01:16 PM
I'm simulating my design which uses the Zynq processing system to read a value from a custom IP core which is essentially a set of memory mapped registers. I'm receiving the following error message:
 : M_AXI_GP0 : *INFO : Reset detected - setting output signals to reset values and checking input signals for correct reset values.
FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover. Process will terminate.
I suspect that the reset signal feeding into my ip core could be the culprit. As I try to simplify the testbench in an attempt to isolate the issue, I'm having trouble understanding the behavior of the processor system reset IP. As shown below: pl_reset is an active high reset signal that feeds into ext_reset_in of the proc_sys_reset.
In my testbench, pl_reset is fixed at 0 for the entire simulation.
However, peripheral_aresetn, which connects to my custom IP core, changes state from 1 to 0 after 2.855 us and my simulation terminates with a FATAL_ERROR.
Another strange behavior is observed on RX_CLK and TX_CLK, the output of the clock wizard, which is shown to be briefly active after the simulation begins; stays quiet until after 2.5 usec and starts to toggle again.
Any help would be greatly appreciated.
03-18-2015 01:42 PM
On Vivado Simulator's behavior, it should not give FATAL_ERROR. Can you please share the design?
03-20-2015 08:07 AM
Please go to portal.iders.ca
Then use the following information to download the entire design:
Claim ID: muZEWYPrVVdYR6Eo
Claim Passcode: 3PtqHW5wNed56HDf
06-12-2015 10:59 AM
I found the problem, apparently when I create an AXI lite custome IP with more 128 registers or more, I get this FATAL ERROR. When i create anything with 64 registers or less, this problem goes away.
06-14-2015 10:51 PM