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Visitor tni
Visitor
9,932 Views
Registered: ‎11-04-2014

Simulating proc_sys_reset and clk_wiz

 

 

I'm simulating my design which uses the Zynq processing system to read a value from a custom IP core which is essentially a set of memory mapped registers. I'm receiving the following error message:

 

 

[105] : M_AXI_GP0 : *INFO : Reset detected - setting output signals to reset values and checking input signals for correct reset values.
FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover. Process will terminate.

 

I suspect that the reset signal feeding into my ip core could be the culprit. As I try to simplify the testbench in an attempt to isolate the issue, I'm having trouble understanding the behavior of the processor system reset IP. As shown below: pl_reset is an active high reset signal that feeds into ext_reset_in of the proc_sys_reset.

Untitled.jpg

 

 

In my testbench, pl_reset is fixed at 0 for the entire simulation.

However, peripheral_aresetn, which connects to my custom IP core, changes state from 1 to 0 after 2.855 us and my simulation terminates with a FATAL_ERROR.

2.jpg

 

Another strange behavior is observed on RX_CLK and TX_CLK, the output of the clock wizard, which is shown to be briefly active after the simulation begins; stays quiet until after 2.5 usec and starts to toggle again.

 Any help would be greatly appreciated.

Thanks,

tni

 

 

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4 Replies
Xilinx Employee
Xilinx Employee
9,927 Views
Registered: ‎09-13-2014

Re: Simulating proc_sys_reset and clk_wiz

On Vivado Simulator's behavior, it should not give FATAL_ERROR. Can you please share the design?

 

--dhiRAj

 

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Visitor tni
Visitor
9,899 Views
Registered: ‎11-04-2014

Re: Simulating proc_sys_reset and clk_wiz

Please go to portal.iders.ca

 

Click, pick-up.

 

Then use the following information to download the entire design:

Claim ID: muZEWYPrVVdYR6Eo
Claim Passcode: 3PtqHW5wNed56HDf

 

Thanks!

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Visitor tni
Visitor
9,128 Views
Registered: ‎11-04-2014

Re: Simulating proc_sys_reset and clk_wiz

I found the problem, apparently when I create an AXI lite custome IP with more 128 registers or more, I get this FATAL ERROR. When i create anything with 64 registers or less, this problem goes away.

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Moderator
Moderator
9,082 Views
Registered: ‎04-17-2011

Re: Simulating proc_sys_reset and clk_wiz

portal.iders.ca is showing Network Error. Can you please check that?
Regards,
Debraj
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