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Observer
Observer
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Registered: ‎04-19-2019

Simulating sub block ip, but not recognized on sources->Hierarchy view

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Hi,

i followed all the step in https://www.xilinx.com/support/answers/60703.html

But my sub block of design_1 that i want to simulate is still not on my hierarchy tree. It is but with the "?".

I did set Hierarchy Update to Automatic Update, Manual Compile Order. 

I tried differents compile ordrering.

The parser can find a component in design_1.vhd and all the sub-components instantiated in it ?

I'm on VIVADO 2018.2.2

Thank you 

Capture.JPGCapture1.JPG

 

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Observer
Observer
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Registered: ‎04-19-2019

Hi @shameera , thanks for your reply.

Actually sometimes i had no error and the simulation ran, but with nothing instantiated...

Now i fixed it, indeed i had the issue AR# 71710 https://www.xilinx.com/support/answers/71710.html

Thanks

Antonin

 

 

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Moderator
Moderator
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Registered: ‎05-31-2017

Hi @antonin_fpga ,

Although it shows the module as missing in the hierarchy window, I think it should be able to run simulation without any errors. Can you please confirm if you are facing any errors while running simulation ?

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Observer
Observer
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Registered: ‎04-19-2019

Hi @shameera , thanks for your reply.

Actually sometimes i had no error and the simulation ran, but with nothing instantiated...

Now i fixed it, indeed i had the issue AR# 71710 https://www.xilinx.com/support/answers/71710.html

Thanks

Antonin

 

 

View solution in original post

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