UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer antonin_fpga
Observer
249 Views
Registered: ‎04-19-2019

Simulating sub block ip, but not recognized on sources->Hierarchy view

Jump to solution

Hi,

i followed all the step in https://www.xilinx.com/support/answers/60703.html

But my sub block of design_1 that i want to simulate is still not on my hierarchy tree. It is but with the "?".

I did set Hierarchy Update to Automatic Update, Manual Compile Order. 

I tried differents compile ordrering.

The parser can find a component in design_1.vhd and all the sub-components instantiated in it ?

I'm on VIVADO 2018.2.2

Thank you 

Capture.JPGCapture1.JPG

 

0 Kudos
1 Solution

Accepted Solutions
Observer antonin_fpga
Observer
185 Views
Registered: ‎04-19-2019

Re: Simulating sub block ip, but not recognized on sources->Hierarchy view

Jump to solution

Hi @shameera , thanks for your reply.

Actually sometimes i had no error and the simulation ran, but with nothing instantiated...

Now i fixed it, indeed i had the issue AR# 71710 https://www.xilinx.com/support/answers/71710.html

Thanks

Antonin

 

 

View solution in original post

0 Kudos
2 Replies
Moderator
Moderator
194 Views
Registered: ‎05-31-2017

Re: Simulating sub block ip, but not recognized on sources->Hierarchy view

Jump to solution

Hi @antonin_fpga ,

Although it shows the module as missing in the hierarchy window, I think it should be able to run simulation without any errors. Can you please confirm if you are facing any errors while running simulation ?

0 Kudos
Observer antonin_fpga
Observer
186 Views
Registered: ‎04-19-2019

Re: Simulating sub block ip, but not recognized on sources->Hierarchy view

Jump to solution

Hi @shameera , thanks for your reply.

Actually sometimes i had no error and the simulation ran, but with nothing instantiated...

Now i fixed it, indeed i had the issue AR# 71710 https://www.xilinx.com/support/answers/71710.html

Thanks

Antonin

 

 

View solution in original post

0 Kudos