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alain_k
Observer
Observer
9,692 Views
Registered: ‎06-27-2014

Simulating/synthesizing Vivado IP Integrator design fails

Hello,

 

I am trying to build a simple BRAM which is shared by the PS and PL. I used Vivado IP Integrator and came up with the following design:

 

Design

I verified the design with no errors and I used "Generate Block Design" and "Create HDL Wrapper" as I intend to connect the BRAM to Verilog code. To check my design, I first tried a simulation and a synthesis without any custom Verilog, but both already caused an error. That one's from the Simulator:

 

ERROR: [VRFC 10-2063] Module <design_1_processing_system7_0_0> not found while processing module instance <processing_system7_0> [/PATH_TO_MY_PROJECT/bd/design_1/hdl/design_1.v:282]

 

Can anybody help me resolving this error?

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9 Replies
vemulad
Xilinx Employee
Xilinx Employee
9,683 Views
Registered: ‎09-20-2012

Hi,

 

Which version of Vivado are you using?

 

Check this article http://www.xilinx.com/support/answers/56492.html

 

Thanks,

Deepika.

Thanks,
Deepika.
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alain_k
Observer
Observer
9,678 Views
Registered: ‎06-27-2014

Hi,

 

I am using the newest version 2014.2 on an Arch Linux 64bit. I checked your link and it says that there would be an orange box next to that module, but there isn't.

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alain_k
Observer
Observer
9,670 Views
Registered: ‎06-27-2014

Yes I've run it. I can see sources and it looks like this:

 

pic.png

Should it look like that?

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alain_k
Observer
Observer
9,637 Views
Registered: ‎06-27-2014

This would be my design. I commented out everything else I've written so far.

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alain_k
Observer
Observer
9,632 Views
Registered: ‎06-27-2014

Ok, I achieved a minor success. I have opened a new project and I've done my design again. Now, I don't get that error anymore. Now I get others. The problem is, that they change everytime I try to simulate or synthesize my design.

 

The tiny piece of Verilog I have written so far:

 

module bram_sample(

    );
    reg [31:0] addr;
    reg [31:0] data;
    reg [3:0]  we;
    
    reg clk;
    reg en;
    reg rst;
    
    design_1_wrapper dsgn
       (.BRAM_PORTB_addr(addr),
        .BRAM_PORTB_clk(clk),
        .BRAM_PORTB_din(data),
        .BRAM_PORTB_en(en),
        .BRAM_PORTB_rst(rst),
        .BRAM_PORTB_we(we));
    
    initial begin
    	addr = 32'd0;
	data = 32'd0;
	we = 4'd0;
	clk = 0;
	en = 0;
	rst = 0;
    end
endmodule

 

The errors I got so far while trying to simulate:

 

ERROR: [XSIM 43-3312] Signal SIGABRT received.

(And I didn't hit cancel or anything like that)

 

[Common 17-49] Internal Data Exception: Design::refreshDesign : Run checkpoint '/PATH_TO_MY_PROJECT/bram_sample.runs/synth_1/bram_sample.dcp' does not exist. Cannot open run.

 

[Common 17-69] Command failed: Failed to compile the design!

 

[Common 17-9] Error reading message records.

 

 

The errors while trying to synthesize:

 

Command: synth_design -top bram_sample -part xc7z020clg400-1
/opt/Xilinx/Vivado/2014.2/bin/loader: line 121: 30708 Segmentation fault "$RDI_PROG" "$@"

(Note that there is a Segmentation fault!!!)

 

[Common 17-69] Command failed: Failed to compile the design!

 

[Common 17-9] Error reading message records.

 

 

Once I even got the design synthesized and implemented, but thats really rarely the case. And I didn't change anything between the runs which gave those errors and the one that worked. The simulation never worked. I really don't know what I'm doing wrong, but when I read Segmentation fault, there must be something terribly wrong. Any suggestions?

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alain_k
Observer
Observer
9,607 Views
Registered: ‎06-27-2014

Does no one have an idea?

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debrajr
Moderator
Moderator
9,552 Views
Registered: ‎04-17-2011

Arch Linux is not a supported OS version to use the tool. Supported OS:
Microsoft Windows Support
• Windows XP Professional (32-bit and 64-bit), English/Japanese
• Windows 7 and 7 SP1 Professional (32-bit and 64-bit), English/Japanese
• Windows 8.1 Professional (64-bit), English/Japanese
Linux Support
• Red Hat Enterprise Workstation 5.8 - 5.10 (32-bit and 64-bit)
• Red Hat Enterprise Workstation 6.4 - 6.5 (32-bit and 64-bit)
• SUSE Linux Enterprise 11.1 - 11.2 (32-bit and 64-bit)
• Cent OS 6.4 and 6.5 (64-bit)

So, one question, did you right click and generate the output products of the BD before running simulation?
Regards,
Debraj
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yashp
Moderator
Moderator
9,527 Views
Registered: ‎01-16-2013

Hello,

Also try :
1) reset output product
2) regenerate output product.

Thanks,
Yash
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kenland
Observer
Observer
9,193 Views
Registered: ‎07-08-2008

In case this is a part of your solution, I am dealing with one of your errors,

 

[Common 17-49] Internal Data Exception: Design::refreshDesign : Run checkpoint '/PATH_TO_MY_PROJECT/bram_sample.runs/synth_1/bram_sample.dcp' does not exist. Cannot open run.

 

This thread http://forums.xilinx.com/t5/Implementation/Synthesis-completes-but-causes-implementation-to-fail/m-p/372587/highlight/false#M7255 says the problem can arise in your synthesis tcl.pre script, IF you are running one.

 

Ken

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