06-28-2019 07:51 AM - edited 06-28-2019 07:53 AM
I'm using Vivado 2018.2
I generated a custom IP template with an AXI4-Stream slave interface. As an example, that template creates an 8-word deep FIFO:
type BYTE_FIFO_TYPE is array (0 to (NUMBER_OF_INPUT_WORDS-1)) of std_logic_vector(((C_S_AXIS_TDATA_WIDTH/4)-1)downto 0);
-- FIFO Implementation FIFO_GEN: for byte_index in 0 to (C_S_AXIS_TDATA_WIDTH/8-1) generate signal stream_data_fifo : BYTE_FIFO_TYPE; begin -- Streaming input data is stored in FIFO process(S_AXIS_ACLK) begin if (rising_edge (S_AXIS_ACLK)) then if (fifo_wren = '1') then stream_data_fifo(write_pointer) <= S_AXIS_TDATA((byte_index*8+7) downto (byte_index*8)); end if; end if; end process; end generate FIFO_GEN;
I created a testbench to fill this fifo with 8 words of data, and the waveforms look ok.
Now I'd like to add some asserts, to check that the fifo indeed contains the written data. So basically I want to view/dump the fifo contents, and eventually make a self-checking testbench.
However, when I look in the Simulation window -> Scope -> Objects, I cannot find the array of 8 word (named 'stream_data_fifo') that actually makes up the fifo:
-> is this expected? Are 'array's never accessible as an object, and is there no way to add them to the the waveform config file? Any other way to verify this from a testbench?
07-03-2019 12:50 AM
Hi @ronnywebers ,
As the signal 'stream_data_fifo' is from the fifo_gen generation block. Can you please try selecting the fifo_gen VHDL block from scope window then check the object window for 'stream_data_fifo' array.