Simulation Behavior fails with Vivado 218.3

[cvasselin]

Good Morning,

My Design has been achieved with Vivado 217.4; now I would like to be compliant with Vivado 218.3. I . Syntesis, Implementation and Bitstream have been correctly done with Vivado 218.3. Unfortunatly Simulation behavior fails. Below an extract of the project_1\project_1.sim\sim_1\behav\xsim\xvlog.log file : 

INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/crvass/Documents/red pitaya/projects/sdr_receiver_DDS/project_1/project_1.ip_user_files/bd/system/ip/system_pll_0_0/system_pll_0_0_clk_wiz.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module system_pll_0_0_clk_wiz
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/crvass/Documents/red pitaya/projects/sdr_receiver_DDS/project_1/project_1.ip_user_files/bd/system/ip/system_pll_0_0/system_pll_0_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module system_pll_0_0
INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/crvass/Documents/red pitaya/projects/sdr_receiver_DDS/project_1/project_1.srcs/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v" into library axi_infrastructure_v1_1_0
INFO: [VRFC 10-311] analyzing module axi_infrastructure_v1_1_0_axi2vector
INFO: [VRFC 10-311] analyzing module axi_infrastructure_v1_1_0_axic_srl_fifo
INFO: [VRFC 10-311] analyzing module axi_infrastructure_v1_1_0_vector2axi
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "C:/Users/crvass/Documents/red pitaya/projects/sdr_receiver_DDS/project_1/project_1.srcs/sources_1/bd/system/ipshared/3b24/hdl/axi_protocol_checker_v2_0_vl_rfs.sv" into library axi_protocol_checker_v2_0_1
INFO: [VRFC 10-311] analyzing module axi_protocol_checker_v2_0_1_axi4litepc_asr_inline
INFO: [VRFC 10-311] analyzing module axi_protocol_checker_v2_0_1_axi4pc_asr_inline
INFO: [VRFC 10-311] analyzing module axi_protocol_checker_v2_0_1_core
INFO: [VRFC 10-311] analyzing module axi_protocol_checker_v2_0_1_syn_fifo
INFO: [VRFC 10-311] analyzing module axi_protocol_checker_v2_0_1_reporter
INFO: [VRFC 10-311] analyzing module axi_protocol_checker_v2_0_1_threadcam
ERROR: [VRFC 10-2989] 'sc_util_v1_0_2_pkg' is not declared [C:/Users/crvass/Documents/red pitaya/projects/sdr_receiver_DDS/project_1/project_1.srcs/sources_1/bd/system/ipshared/3b24/hdl/axi_protocol_checker_v2_0_vl_rfs.sv:5485]
ERROR: [VRFC 10-2865] module 'axi_protocol_checker_v2_0_1_threadcam' ignored due to previous errors [C:/Users/crvass/Documents/red pitaya/projects/sdr_receiver_DDS/project_1/project_1.srcs/sources_1/bd/system/ipshared/3b24/hdl/axi_protocol_checker_v2_0_vl_rfs.sv:5453]
INFO: [VRFC 10-311] analyzing module axi_protocol_checker_v2_0_1_top
ERROR: [VRFC 10-2865] module 'axi_protocol_checker_v2_0_1_top' ignored due to previous errors [C:/Users/crvass/Documents/red pitaya/projects/sdr_receiver_DDS/project_1/project_1.srcs/sources_1/bd/system/ipshared/3b24/hdl/axi_protocol_checker_v2_0_vl_rfs.sv:5858]

[drjohnsmith]

ERROR: [VRFC 10-2989] 'sc_util_v1_0_2_pkg' is not declared

[dpaul24]

@cvasselin,

The problem is pointed out in the above post.

Syntesis, Implementation and Bitstream have been correctly done with Vivado 218.3. Unfortunatly Simulation behavior fails.

Because I suspect the SV unit is part of the test-bench.

ERROR: [VRFC 10-2865] module 'axi_protocol_checker_v2_0_1_top' ignored due to previous errors [C:/Users/crvass/Documents/red pitaya/projects/sdr_receiver_DDS/project_1/project_1.srcs/sources_1/bd/system/ipshared/3b24/hdl/axi_protocol_checker_v2_0_vl_rfs.sv:5858]

[cvasselin]

How to fix this ?

Best Regards,

[drjohnsmith · Accepted solution]

code says it can not find 'sc_util_v1_0_2_pkg' 

check it exists in the folder , added to the project,

       try removing it fomr the project and re adding,