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Contributor
Contributor
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Registered: ‎06-25-2014

Simulation ERROR - Failure: ERROR:add_1 must be in range [-1,DEPTH-1]

While using Vivado 2016.4 simulating a design with a Xilinx IP Complex Multiplier (xilinx.com:ip:cmpy:6.0) in it I came across this error..

ERROR:add_1 must be in range [-1,DEPTH-1]

..with no other information as to what was causing the problem. It was only by searching for the error message on the internat I came across this post which helped me cure the problem..

https://forums.xilinx.com/t5/Simulation-and-Verification/ERROR-add-1-must-be-in-range-1-DEPTH-1/td-p/847930

..Unfortunately the solution was to reset the signals going into this block of IP. These resets would appear to be only required for simulation and so are against the rules regarding reseting signals in the Ultrafast Methodology.

Why is the error message so useless for debugging and why does simulating this IP require these unnecessary resets?

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