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Visitor
Visitor
625 Views
Registered: ‎10-02-2020

Simulation Error - NewBie Misstakes?

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Hi,

I'm NewBie about FPGA and Xilinx. I was watching a tutorial and there is a code related to 4-bit adders. So I want to simulate that code but some errors popped.

I'm not sure is it because of the codes or configuration or related with Vivado.

1.JPG2.JPG3.JPG

and in elaborate.log file

Vivado Simulator 2020.1
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: E:/Vivado/Vivado/2020.1/bin/unwrapped/win64.o/xelab.exe -wto 6c22de928ece405b955c9f2b54b9c079 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Add4_behav xil_defaultlib.Add4 -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel

I didn't quite understand what is going on at this moment.

Can anybody help me with it, please?

*Note: I hope I posted the correct place now. and sorry if any of my writes seem rude. My native language is not English.

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1 Solution

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Explorer
Explorer
398 Views
Registered: ‎01-27-2008

Hi @SerkanKas 

Since you're clearly new I'll give an example of exactly what these folks are saying for your system. I abandoned VHDL for SV years ago, so the testbench is in systemverilog.

You can't have a system and simulate it without a testbench (at least in Xsim, Vivado's simulator - easily). In modelsim you can use "force files" TCL - scripting that forces inputs to provide outputs. Perhaps that exists in Vivado / Xsim as well but I've never decided to find out.

So here's an example testbench.

module add4_tb();

   // this is because the model preprends zero instead of sign extends
   logic unsigned [3:0] d1, d2, sum;

   logic                cin, cout;

   initial begin
      d1 = 0; d2 = 0; cin = 0;
      #10;
      d1 = 7; d2 = 7; cin = 0;
      #10;
      d1 = 7; d2 = 7; cin = 1;
      #10;
      d1 = 9; d2 = 0; cin = 1;
      #10;
      d1 = 0; d2 = 9; cin = 0;
      #10;
     // add more statements here to further test (note cout isn't tested yet)
   end

   // anytime there's a change detected, post it
   always_comb
     begin
        $display("[@%5t]  d1: %2d   d2: %2d  cin: %d  ||  sum: %2d  cout: %d", $time, d1, d2, cin, sum, cout);
     end
   // this "instantiates" the adder into the testbench, wiring it up
   //    against the testbench signals
   add4 uut
   ( .data1(d1), .data2(d2), .cin(cin), .cout(cout), .sum(sum));
        
endmodule

You should be able to load this file into a new vivado project with your adder (note the name change of the entity to add4) and get these results.

 

And a waveform matching.

olupj_0-1602116408661.png

I hope you expand this for other systems and have fun exploring this world of hardware design using hardware description languages.

Have fun,

Jerry

 

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7 Replies
617 Views
Registered: ‎07-23-2019

 

What is in your testbench?

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Visitor
Visitor
550 Views
Registered: ‎10-02-2020

I'm sorry, I didn't get your question.

What do you mean by "what is in your testbench?"

What would you like to learn?

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Scholar
Scholar
537 Views
Registered: ‎08-01-2012

You simply posted the code for an entity called ADD4 and a waveform. Something needs to be driving the add4 module in the simulator, and this would usually be a testbench. Can you post your testbench code?

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Xilinx Employee
Xilinx Employee
492 Views
Registered: ‎08-10-2015

Hi @SerkanKas,

 

Can you please share the design for further understanding and to find out design or tool issue.

 

Thanks,

Sunilkumar

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Visitor
Visitor
467 Views
Registered: ‎10-02-2020

this is all the code I wrote so far. So there should be more code?

Best I should watch a couple more videos to understand better I guess. Thanks for now, if I had any issue I'll ask.

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Visitor
Visitor
429 Views
Registered: ‎09-18-2020

You have already created a model for a circuit, but you don't have anything driving the inputs of the model. A testbench is another piece of code that instantiates the model you have created, and drives the inputs of the model, so you can see if its behaving the way you want it to. The test bench is typically in the same language as the model, and is not something you run through synthesis and program into a device. Its only for test, hence the name test bench.

Rob Swan | FPGA Design & Support Engineer – E3 | DesignLinx Solutions
https://www.designlinxhs.com
Explorer
Explorer
399 Views
Registered: ‎01-27-2008

Hi @SerkanKas 

Since you're clearly new I'll give an example of exactly what these folks are saying for your system. I abandoned VHDL for SV years ago, so the testbench is in systemverilog.

You can't have a system and simulate it without a testbench (at least in Xsim, Vivado's simulator - easily). In modelsim you can use "force files" TCL - scripting that forces inputs to provide outputs. Perhaps that exists in Vivado / Xsim as well but I've never decided to find out.

So here's an example testbench.

module add4_tb();

   // this is because the model preprends zero instead of sign extends
   logic unsigned [3:0] d1, d2, sum;

   logic                cin, cout;

   initial begin
      d1 = 0; d2 = 0; cin = 0;
      #10;
      d1 = 7; d2 = 7; cin = 0;
      #10;
      d1 = 7; d2 = 7; cin = 1;
      #10;
      d1 = 9; d2 = 0; cin = 1;
      #10;
      d1 = 0; d2 = 9; cin = 0;
      #10;
     // add more statements here to further test (note cout isn't tested yet)
   end

   // anytime there's a change detected, post it
   always_comb
     begin
        $display("[@%5t]  d1: %2d   d2: %2d  cin: %d  ||  sum: %2d  cout: %d", $time, d1, d2, cin, sum, cout);
     end
   // this "instantiates" the adder into the testbench, wiring it up
   //    against the testbench signals
   add4 uut
   ( .data1(d1), .data2(d2), .cin(cin), .cout(cout), .sum(sum));
        
endmodule

You should be able to load this file into a new vivado project with your adder (note the name change of the entity to add4) and get these results.

 

And a waveform matching.

olupj_0-1602116408661.png

I hope you expand this for other systems and have fun exploring this world of hardware design using hardware description languages.

Have fun,

Jerry

 

View solution in original post

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