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Contributor
Contributor
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Registered: ‎04-17-2014

Simulation IP from Vivado 2014.1

I created a FIFO called "fifo_16x128" using the IP catalog in  Vivado 2013.4. Vivado reported that two files were needed to support simulation: "fifo_16x128.vhd" and "fifo_generator_v11_0.vhd".   With these two files I am able to simulate the design within Aldec by compiling  "fifo_generator_v11_0.vhd" into a library called  "fifo_generator_v11_0" so that  "fifo_16x128.vhd" can find what it needs in the library and compile correctly.

 

Now, I have updated to 2014.1.  I regenerated the core but now it reports only one file is needed for simulation: "fifo_16x128.vhd".  However, the file  "fifo_16x128.vhd" calls for the library "fifo_generator_v12_0" but the vhdl source file for this is nowhere to be found.

 

How do I simulate the v12 FIFO design within Aldec?

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2012

Re: Simulation IP from Vivado 2014.1

Hi,

 

Contact Aldec Support as mentioned in release notes: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug973-vivado-release-notes-install-license.pdf (page no. 17)

 

Thanks,

Vinay 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

Re: Simulation IP from Vivado 2014.1

How did you have Vivado report the files used in simulation? with "report_compile_order" command?

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Registered: ‎12-07-2009

Re: Simulation IP from Vivado 2014.1

Hi David

 

Read the user guide ug900 for better comprehension about simulating Vivado IPs and using the libraries.

In a nutshell, what used to be inside the library "xilinxcorelib" in ISE (e.g. higher level models such as FIFO Generator) is no longer provided as a library and the user needs to compile the files himself.

 


@david.mcdaniel wrote:
However, the file  "fifo_16x128.vhd" calls for the library "fifo_generator_v12_0" but the vhdl source file for this is nowhere to be found.

 

How do I simulate the v12 FIFO design within Aldec?


If you search for it you should find it easily.

It will usually be located inside a folder such as :

<my_vivado_project_name>.srcs/sources_1/ip/<my_fifo_name>/fifo_generator_v12_0/

You will find several versions of the model, basically a behavioral model and a structural netlist.

 

PS: note that I have not yet simulated with 2014.1. I have just updated my IPs and check that the simulation models where still at the same place.

 

Sam

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Moderator
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Registered: ‎04-17-2011

Re: Simulation IP from Vivado 2014.1

If your design includes IP generated from the Vivado IP catalog (IP.xci), you do not need the XilinxCoreLib library for simulation. Simulation models of Xilinx Vivado IP cores are delivered as an output product when the IP is generated. 
Also, when you use compile_simlib to compile the Xilinx Libraies for 3rd party simulators, the simulation models for the Vivado IP cores are not included in the pre-compiled XilinxCoreLib libraries.
 
If in case your design contains legacy ISE CORE Generator IP used in Vivado, you still have XilinxCoreLib libraies to support simulating them.
These files could be seen under:
$XILINX_VIVADO\ids_lite\ISE\verilog\src\XilinxCoreLib 
$XILINX_VIVADO\ids_lite\ISE\vhdl\src\XilinxCoreLib
 
where XILINX_VIVADO = Path of installed Vivado tool.
Regards,
Debraj
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Registered: ‎04-07-2008

Re: Simulation IP from Vivado 2014.1

It appears the $XILINX_VIVADO\ids_lite\ISE\verilog\src\XilinxCoreLib and $XILINX_VIVADO\ids_lite\ISE\vhdl\src\XilinxCoreLib have been removed from the 2014.1 installation. They were part of the 2013.4 release. Is their removal intentional?

I just ran into this myself trying to simulate a design with legacy ISE coregen models under Vivado Simulator in 2014.1.
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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

Re: Simulation IP from Vivado 2014.1

Yes, we've stopped shipping XilinxCoreLib and EDK libs with ISE lite. The last Vivado release for customer using Coregen IP is 2013.4 and customers using 2014.1 should upgrade the IP to XCI.

 

If you have an existing test that uses xilinxcorelib or xilinxcorelib_ver, you will need to update your test to create your own local xilinxcorelib or xilinxcorelib_ver by compiling the right IP sources.

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Visitor
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Registered: ‎06-22-2012

Re: Simulation IP from Vivado 2014.1

I ran into the same problem today.

 

 

When I used an external simulator, I was able to use the simulation libraries compiled from 2013.4. I created a rather large IP Core using VivadoHLS, the testbench I use for power evaluation still had old ISE IP Cores. However, I simply specified the libs I compiled for 2013.4 for Questa and the simulation could be compiled and ran through as expected.

 

It is sufficient for rudimentary testing, otherwise I would not recommend this approach. 

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Registered: ‎03-26-2012

Re: Simulation IP from Vivado 2014.1

I am also experiencing issues with generating FIFO IP with Vivado 2014.1.

 

When I generated the FIFO IP core (named test_fifo_2013_4) using Vivado 2013.4 in a managed IP project, it listed 2 files as Simulation files in the Sources sub-window: test_fifo_2013_4.v and fifo_generator_v11_0.v. Also these are Verilog non-encrypted simulation files since I set the simulator language as Verilog and I can compile these files with Modelsim 10.2c. The paths for these files are:

test_fifo_2013_4/sim/test_fifo_2013_4.v

test_fifo_2013_4/fifo_generator_v11_0/simulation/fifo_generator_v11_0.v

 

When I try the same FIFO IP core (now named test_fifo_2014_1) using Vivado 2014.1, it only lists 1 file as Simulation file: test_fifo_2014_1.vhd. This is a VHDL non-encrypted simulation file, even though I set the simulator language as Verilog. I get the warning in TCL console:

 

WARNING: [IP_Flow 19-1687] The current project language is set to Verilog. However IP 'test_fifo_2014_1' does not support 'Verilog Simulation' output products, delivering 'VHDL Simulation' output products instead.

Even though the fifo_generator_v12_0 module is not available listed as a simulation source, it is available in the generated files with a different file name. The path for the generated simulation files are now:

test_fifo_2014_1/sim/test_fifo_2014_1.vhd (unencrypted VHDL file)

test_fifo_2014_1/fifo_generator_v12_0/simulation/fifo_generator_vhdl_beh.vhd (encrypted VHDL file)

 

Strangely, even though Vivado has warned that Verilog simulation output products do not exist, fifo_generator_v12_0 is available as a Verilog module with the path:

/tools/xilinx/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/simulation/fifo_generator_vlog_beh.v

 

I am trying to compile the new VHDL files but neither of them compile with Modelsim. I get the following error when trying to compile test_fifo_2014_1/sim/test_fifo_2014_1.vhd:

 

> vcom test_fifo_2014_1/sim/test_fifo_2014_1.vhd
Model Technology ModelSim SE-64 vcom 10.2c Compiler 2013.07 Jul 18 2013
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
** Error: test_fifo_2014_1/sim/test_fifo_2014_1.vhd(56): Library fifo_generator_v12_0 not found.
** Error: test_fifo_2014_1/sim/test_fifo_2014_1.vhd(57): (vcom-1136) Unknown identifier "fifo_generator_v12_0".
** Error: test_fifo_2014_1/sim/test_fifo_2014_1.vhd(59): VHDL Compiler exiting

 

And the following error is returning when trying to compile test_fifo_2014_1/fifo_generator_v12_0/simulation/fifo_generator_vhdl_beh.vhd:

 

> vcom test_fifo_2014_1/fifo_generator_v12_0/simulation/fifo_generator_vhdl_beh.vhd
Model Technology ModelSim SE-64 vcom 10.2c Compiler 2013.07 Jul 18 2013
-- Loading package STANDARD
** Error: test_fifo_2014_1/fifo_generator_v12_0/simulation/fifo_generator_vhdl_beh.vhd(46)): in protected region.
** Error: test_fifo_2014_1/fifo_generator_v12_0/simulation/fifo_generator_vhdl_beh.vhd(46)): in protected region.
** Error: test_fifo_2014_1/fifo_generator_v12_0/simulation/fifo_generator_vhdl_beh.vhd(46)): in protected region.
** Error: test_fifo_2014_1/fifo_generator_v12_0/simulation/fifo_generator_vhdl_beh.vhd(46)): in protected region.

 

The file /tools/xilinx/Vivado/2014.1/data/ip/xilinx/fifo_generator_v12_0/simulation/fifo_generator_vlog_beh.v compiles with any error.

 

What can I do about the errors I am getting when trying to compile the generated files?

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Scholar
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Registered: ‎12-07-2009

Re: Simulation IP from Vivado 2014.1

I have been using a custom simulation environment  using Modelsim for some years and I'm not used to launch simulation from ISE/Vivado. I use compxlib/ compile_simlib to make the necessary primitive libraries (unisim, etc.) and IP core libraries (xilinxcorelib).

 

The fact that in Vivado, the user has to build the xilinxcorelib component (FIFO_GENERATOR_V12_0 etc...) himself by compiling the appropriate sources provided in the instantiated IP folder is really unconvenient to say the least.

I had a hard time figuring out what went wrong when I tried to do it myself.

 

The main reason is that these are mostly encrypted files, so if something goes wrong you basically get

"error nofile (<line_number>) protected area." Also there are a lot of mixed sources (VHDL and Verilog) for the behavioral models, though you may overcome this by using the funcsim model which is a netlist of the IP in your prefered language (set in the Vivado project preferences) but it runs way slower.

 

I finally used the Vivado simulation script file

located at <project_name>/<project_name>.sim/sim_1/behav/<top_module_name>.do

to check how the "xilinxcorelib" libraries such as FIFO_GENERATOR or XBIP_DSP_MACRO_V3_0 were supposed to be compiled and it seems that the compile order as well as the library name cannot be changed. So at least for these IP libraries, the user should copy the simulation script provided by Vivado.

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Registered: ‎04-17-2011

Re: Simulation IP from Vivado 2014.1

If you upgrade your IP's to 2014.1 then also you are seeing this issue? Did you do that already?
Regards,
Debraj
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Registered: ‎12-07-2009

Re: Simulation IP from Vivado 2014.1

I upgraded all my IPs (using Report IP in Vivado) to their latest version in 2014.1, and then tried to simulate. At first it did not work and as I said in the previous post, it was hard to figure out why.

 

Now it works and as I said in the previous post, I get errors when the compile order or the library name isn't the same as the one in the simulation script made by Vivado (in the case of the library name, I did not try to change it in Vivado 2014, just with 2013.3).

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Re: Simulation IP from Vivado 2014.1

@ samcossais: I also generated an IP example design project for my test FIFO and then ran Modelsim from Vivado. But the .do file that was created in "<project_name>/<project_name>.sim/sim_1/behav/" folder lists the "<IP_name>_funcsim.v" for compilation. As you said, this makes simulation very slow.

 

Do you get the behavioural model listed in your .do file?

 

@ debrajr: I am using Vivado 2014.1 and get the issues I listed in my post here.

 

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Registered: ‎12-07-2009

Re: Simulation IP from Vivado 2014.1


@shahid.nasim wrote:

@ samcossais: I also generated an IP example design project for my test FIFO and then ran Modelsim from Vivado. But the .do file that was created in "<project_name>/<project_name>.sim/sim_1/behav/" folder lists the "<IP_name>_funcsim.v" for compilation. As you said, this makes simulation very slow.

 

Do you get the behavioural model listed in your .do file?

 


Yes. It uses the file in the /sim/ folder of the IP, not the funcsim one. I selected behavioral simulation when launching it from Vivado.

The main is reason for you to get a funcsim file used instead is explained in ug900 (I don't remember which page). In fact the simulation models used for the IP depends on what language you chose for your simulator in the Vivado simulation settings. In the case of the FIFO generator IP, only VHDL is supported for the behavioral model, so if you chose Verilog only for the simulator language you will only get the funcsim model (which is available for both languages). If you choose mixed, you will always get the behavioral model + the funsim model.

 

Also, there is no relation but I changed a few things in the simulation settings in Vivado, including "use fast simulation libraries" (e.g "unifast" is used instead of "unisim" for some models, whose limitations are explained in ug900).

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Registered: ‎04-17-2011

Re: Simulation IP from Vivado 2014.1

@ debrajr: I am using Vivado 2014.1 and get the issues I listed in my post here.

For the error's you are seeing, the IP files generated for FIFO are encyrpted. Hence, when you generate output products, it does synthesize the IP and uses a write_verilog/write_vhdl to generate the _funcsim.vhd/.v file. This file should be used for simulation in any third party simulator.

But I would suggest you to check it once in 2013.4 where Xilinxcorelib is present when you do compile_simlib.
Regards,
Debraj
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Re: Simulation IP from Vivado 2014.1


to generate the _funcsim.vhd/.v file. This file should can? be used for simulation in any third party simulator.


 

debrajr >

As shahid.nasim and I both said, the simulation is slower if we use the funscim model instead of the behavioral model. If you only want a behavioral simulation the above statement is false in my humble opinion (check out my post) and the "should" might be replaced by a "can". It can be used in any case but it will be slower.

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Re: Simulation IP from Vivado 2014.1

I would suggest having a look at chapter-6 of the guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_4/ug896-vivado-ip.pdf

The simulation model delivered by IP is required for simulation. The slowness could be a seperate issue and can be attributed by the size of the IP because it is nothing but the structural model of IP. 

Regards,
Debraj
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Re: Simulation IP from Vivado 2014.1


@debrajr wrote:

I would suggest having a look at chapter-6 of the guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_4/ug896-vivado-ip.pdf


This chapter 6 says exacty what I said in my previous post (though I said it was explained in ug900). In a nutshell, if you set the simulator language to "mixed" you will always be able to use the behavioral model.


@debrajr wrote:

The simulation model delivered by IP is required for simulation. The slowness could be a seperate issue and can be attributed by the size of the IP because it is nothing but the structural model of IP. 


On a separate post (http://forums.xilinx.com/t5/Simulation-and-Verification/SRIO-Gen2-netlist-models-slow-behavioral-models-encrypted/m-p/435162) I have been told the structural model (funcsim) is slower than the behavioral one and in practice it was the case. And this is to be expected as the funcsim model is a structural model unlike the behavioral model, which is much less detailed and thus much faster.

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Re: Simulation IP from Vivado 2014.1

@samcossais : I was trying to open Modelsim from Vivado 2014.1 with Verilog set as simulator language. After setting simulator language to Mixed, I finally see the list of behavioral model VHDL files that need to be compiled. Thanks for that tip.

 

There are in fact quite a lot of VHDL files, making it more difficult than simply compiling one file, as was the case with Vivado 2013.4, where a single unencrypted Verilog behavioral model file was generated: <IP_name>/simulation/<IP_name>.v. This file contained multiple modules in a single file. I guess in the latest Vivado, these modules have been separated into different files.

 

So with the new .do file that is created, the important steps seem to be:

vmap fifo_generator_v12_0 work

This adds a line in modelsim.ini and without it, the VHDL compilation gives the error I got earlier when trying to compile test_fifo_2014_1/fifo_generator_v12_0/simulation/fifo_generator_vhdl_beh.vhd. The other thing is exactly maintaining the compile order that is listed in the .do file. This seems to be when a VHDL module is dependent on other modules or packages.

 

@ debrajr:  I used fifo_generator_v11_0 in Vivado 2013.4 and as I said, I only needed to compile a single unencrypted Verilog behavioral model file: fifo_generator_v11_0/simulation/fifo_generator_v11_0.v.

 

I have seen that the structural model is usually slower than the behavioural and I assume this is because it uses low-level primitive instantiations instead of high-level logic.

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Registered: ‎12-07-2009

Re: Simulation IP from Vivado 2014.1

I actually made a different topic about IP files size, as models such as blk_mem_gen_v8_2 are copied for every IP generated :

http://forums.xilinx.com/t5/Design-Entry/Vivado-2014-1-IP-any-way-to-reduce-disk-space/td-p/459698

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Observer
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Registered: ‎05-28-2009

Re: Simulation IP from Vivado 2014.1

I have a similar question. I'm just trying to customize the IP in a Vivado Manage IP project, just like we used to do with coregen. I run modelsim independently of Vivado. I've generated the output products, it seems like I can either use the structural _funcsim.vhd file, or I can compile all the libraries it spits out (which is ~200 files for a floating point core). I can't seem to generate a .do file from the manage IP folder, but I can at least get the compile order from report_compile_order.

 

So, if I want to do a behaviorial sim, I want to get the .do file generated to make things as automated as possible. Do I actually have to create a full Vivado PAR project to do this?

 

The funcsim model doesn't seem to work with me, I know the error messages are opaque if something's wrong so I'm not sure that's no my fault. But that is typically slower also.

 

Do I really have to set up a full Vivado project just to simulate a small piece of IP?

 

Thanks.

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Registered: ‎04-17-2011

Re: Simulation IP from Vivado 2014.1

You can take up any example Vivado project with IP and run Modelsim simulation from GUI (Use all steps - Behavioral, Funcsim, Timing). That generates .do files for you. Copy it over to the other location and then modify it as per your need. This way you need not create a Vivado project again and again (but the condition is you have all the IP files generated properly).
Regards,
Debraj
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Re: Simulation IP from Vivado 2014.1

This shows how necessary a "XilinxCoreLib" is and how unconvenient it is without it. Either you make these higher level IP libraries very easy to compile at a local level (but it still use disk space at every instance so it would still be not too good) or you keep it in a common library folder built by a wizard prodived with Vivado. The second solution was what was done in ISE, I don't understand why you changed that.

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Re: Simulation IP from Vivado 2014.1

I think there is a simple solution Xilinx could deploy for this use case. The hooks are already in place. When you have a normal Vivado Implementation project, it can generate a .do file or actually run modelsim to compile all the libraries for IP in the project, it puts them under an msim folder.

 

This function should be available in a Manage IP project. Ideally, it could even ask for a disk location you want to compile the libraries too (much like compxlib used to), but it would only have to compile libraries used by IP in the Manage IP project.

 

Then, you could create a Manage IP project, customize your IP, and compile all the needed libraries to a path on your drive, for vmapping in modelsim external to Vivado.

 

It seems like right now, to do this, after customizing the IP in Manage IP, I then have to make a second, normal, Vivado project, from which I can run the modelsim behavioral sim to compile these libraries, then manually copy the msim folder to my separate libraries folder. Being able to do this from the Manage IP project directly would eliminate most of the headaches of this approach.

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Re: Simulation IP from Vivado 2014.1

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Re: Simulation IP from Vivado 2014.1

Thanks for all the comments. There has been a lot of internal discussion on this topic too.

We are looking at it from multiple angles from the IP source code optimization angle, the language angle (most new IP will only be in Verilog/SystemVerilog), the concatenation angle, the incremental compile angle for simulators to see how can we get to a good solution here.

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Re: Simulation IP from Vivado 2014.1

@graces I'm glad that Xilinx understand that this is an issue that needs resolved. Can we expect to see any improvement in the next release, or are we stuck with this for a while yet? Using basic building blocks needs to be easy and at the moment it's not. ISE was way better in this respect.

You mention another bug bear, Xilinx seem to be dropping VHDL support in IP as time goes on. This is also disappointing for our company as we use VHDL, as I'm sure a lot of your customers do.

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Re: Simulation IP from Vivado 2014.1

Dear All,

 

While simulating from questa 10.2c, I was also getting error '... protected region' from FIFO IP with Vivado 2013.4 and 2014.2 too. After spending copule of hours and reading ug896-vivado-ip ch#6, found that the error was, because of not pointing correct path of libraries which are required for Xilinx FIFO IP, e.g. unisim, simprim, in modelsim.ini file.

 

So, we should make sure that, per ug896-vivado-ip ch#6, all xilinx libraries paths are correct in modelsim.ini file.

Hope, this can resolve error "... protected region' from FIFO IP.

 

Regards,

pkaushik

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Re: Simulation IP from Vivado 2014.1

Hi

Well modesim.in is used to make the Modelsim project file (.mpf) so you can also modify your mpf file or use the library commands to modify the paths. The way the libraries are compiled seems to be very important, especially the name of the library and the order, hence my previous  comment about it, and the fact that one should check the simulation script (top_file.do) generated by the Vivado simulator.

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Re: Simulation IP from Vivado 2014.1

Our project contains about 60 different testbenches written in VHDL. Behavioral simulations using these testbenches are carried out every night as part of the automated regression testing. The 60 testbenches result in over 100 simulations as some testbenches are simulated several times with different stimuli data. The nightly regression runs are always run on a clean checkout from the version control repository containing only the source code and no intermediate artifacts to ensure reproducability. Our source code is highly structured such that the verification scripts can automatically compile and run simulations with no user intervention.

 

When atempting to transition our project from ISE to Vivado a big problem has surfaced regarding how the Xilinx generated IP-blocks can be compiled by our verficiation scripts for our nightly regressions. Using ISE the mechanism was simple. We generated the IP-blocks using the Core Generator and commited only three files to our version control, .xco, .vhd, .ngc. The .xco file to be able to reconfigure the IP, the .vhd file for behavioral simulation and the .ngc file for implementation. We only use simple 'bread and butter' IP blocks such as block rams, fifo:s, floating point blocks and dividers.

 

With the ISE solution it was simple for our verficiation scripts to just compile the single .vhd file for behavioral simulation. The .vhd file would simply instantiate a component from the xilinxcorelib. With Vivado however it seems the xilinxcorelib has been removed and it is no longer clear what to compile to be able to perform behavioral simulation using the Xilinx IP-cores. Even a simple IP-core generates a huge recursive structure of behavioral simulation models corresponding to the deprecated xilinxcorelib. Manually running the simulator from the Vivado GUI as the only way to compile the IP is not an option for automated regression tests and does not scale to the needs of serious verification efforts in large FPGA projects.