09-04-2014 01:02 AM
With Vivado however it seems the xilinxcorelib has been removed and it is no longer clear what to compile to be able to perform behavioral simulation using the Xilinx IP-cores. Even a simple IP-core generates a huge recursive structure of behavioral simulation models corresponding to the deprecated xilinxcorelib.
I almost totally agree with you. However there is still a way to compile de Xilinx IPs manually (and make your own xilinxcorelib). But it is quite hard because the files needed seems to depend on compile order and library names (+they are encrypted). The best way is to run the Vivado sim script once and copy some parts of its code to make your own xilinxcorelib. Then you will be able to reuse the lib for any bench you have.
But yes, as I said in my other posts, I totally agree that having no IP library is absolutely nonsense (and should have been nonsense from Xilinx point of view too).
09-17-2014 05:33 PM
Thank you for your comments samcossais et al. I share your disappointment that Xilinx did not foresee (or did not care about) the adverse impacts on its paying customers. We had a great system under ISE, with readable, usable behavioral models of the cores, which greatly facilitated debug and design verification, and which could be quickly run on anyone's simulator.
09-26-2014 04:31 PM
I came across this thread because I'm in Vivado 2014.1 and .2, and I thought it would be easy (and better) to use a Xilinx IP FIFO, as opposed to the roll-my-own method Wow, this is painful. As someone coming from that other FPGA company, I'm used to Quartus Megawizard IP, where creating a FIFO was as easy as: 1) GUI to get file wrappers, 2) use those wrappers and the provided library. In Vivado, I'm having to complete the design source with the new FIFO, then generate full sim models with all these files, just so I can get a file order to use in an external simulator?
09-29-2014 08:46 PM
After a solid day of debug of trying to get this to work with Cadence IES, I realized a few things:
1) If Vivado generated Verilog, then all you would need is the file order from Vivado .do and .sh files for IES.
2) However, if Vivado has to generate VHDL (for FIFOs) then the files it creates have VHDL library information (library.entity.architecture,) and this has to match the Cadence cds.lib library names. Also, some of those files become protected, which makes compile debug challenging. In this case, you have to compile files from Vivado's IES .sh file exactly as they were generated, so the correctly named libraries are created for Cadence IES that match the VHDL. You can then pull these libraries into IES (irun) using -reflib